Dr. Eishi Arima

Chair of Computer Architecture and Parallel Systems
Department of Informatics
Technical University of Munich

Email: eishi.arima 'at' tum.de

Research Interests

  • Computer architecture and parallel systems
  • Power-aware computing
  • Process and resource management in HPC systems
  • Heterogeneous systems
  • Memory and storage systems
  • Performance modeling, analysis, and optimization
  • Hardware/software codesign
  • Processor microarchitectures

Student Research Opportunities

If you are looking for bachelor's/master's thesis (or guided research) topics and are interested in one or more of the above research areas, don't hesitate to contact me.

Academic Services

  • Organizing Committee: HPCAsia'22 (Track Chair); ACM CF'21 (Special Session Co-Chair); ACM CF'20 (Program Co-Chair); IEEE Cluster'19 (Proceedings Chair); IEEE NVMSA'18 (Web Chair)
  • Program Committee: IEEE HiPC'22; CANDAR'22; xSIG 2022 (Japan domestic); IEEE NVMSA'22; ACM CF'22; IEEE IPDPS'22; CANDAR'21; IEEE NVMSA'21; ISC'21 PhD Forum; xSIG 2021 (Japan domestic); IEEE IPDPS'21 (system software track); IEEE IPDPS'21 (programming model track); HPCAsia'21; IEEE HiPC'20; IA^3@SC'20; CANDAR'20; IEEE Cluster'20 (posters); ISC'20 PhD Forum; xSIG 2020 (Japan domestic); CANDAR'19; ISC'19 PhD Forum; xSIG 2019 (Japan domestic); CANDAR'18; ICPP'18; IEEE NVMSA'18; SCAsia'18; HPCAsia'18; CANDAR'17; IEEE NVMSA'17
  • Journal Reviews: Journal of Parallel and Distributed Computing (2021); Concurrency and Computation: Practice and Experience, Wiley (2021); The Journal of Supercomputing, Springer (2020-); Elsevier Integration, the VLSI Journal (2019); IPSJ Transactions on Advanced Computer Systems (2017-); IEICE Transactions on Information and Systems (2016-)

Student Mentoring

(Completed Only)

  • [Master Thesis]: Faith, Rifiq Al "Optimizing Memory Capacity/Bandwidth Priorities on Modern CPU via Machine Learning"
  • [Master Thesis]: Stobbe, Adrian "Dealing with Resource Limits for a HPC Jobs in a Distributed System"
  • [Master Thesis]: Saba, Issa "Job Co-location and Power Budgeting for Heterogeneous HPC Systems"
  • [Master Thesis]: Terkin, Tuana "Memory-footprint aware co-scheduling for HPC clusters"
  • [Guided Research]: Krisko, Milan "Probabilistic Hardware Performance Counters"
  • [Bachelor Thesis]: Kang, Minjoon "Co-scheduling for Modern GPUs under Power Caps"
  • [Bachelor Thesis]: Balakirev, Aleksandr "Exploring the Benefits of Non-volatile Memory in HPC Applications" (Led by Dr. Josef Weidendorfer)

Publications and Talks

  • Issa Saba, Eishi Arima, Dai Liu, Martin Schulz "Orchestrated Co-Scheduling, Resource Partitioning, and Power Capping on CPU-GPU Heterogeneous Systems via Machine Learning" In Proceedings of 35th GI/ITG International Conference on Architecture of Computing Systems (ARCS), pp.xxx-xxx, Sep. (2022) (to appear)
  • Eishi Arima, Minjoon Kang, Issa Saba, Josef Weidendorfer, Carsten Trinitis, Martin Schulz "Optimizing Hardware Resource Partitioning and Job Allocations on Modern GPUs under Power Caps" In Proceedings of International Conference on Parallel Processing Workshops, pp.xxx-xxx, Aug. (2022) (to appear)
  • Eishi Arima, Isaías Comprés, Martin Schulz "On the Convergence of Malleability and the HPC PowerStack: Exploiting Dynamism in Over-Provisioned and Power-Constrained HPC Systems" In Proceedings of ISC High Performance Workshops, pp.xxx-xxx, Jun. (2022) (to appear)
  • Eishi Arima, Carsten Trinitis, Martin Schulz "Toward Dynamic Orchestration of Data/Power/Process Management for Hybrid Memory Based Systems" In FGBS, 3pages, Sep. (2021)
  • Eishi Arima, Yuetsu Kodama, Tetsuya Odajima, Miwako Tsuji, Mitsuhisa Sato "Power/Performance/Area Evaluations for Next-Generation HPC Processors using the A64FX Chip," In Proceedings of IEEE Symposium on Low-Power and High-Speed Chips and Systems, 6pages, Apr. (2021)
  • Yuetsu Kodama, Tetsuya Odajima, Eishi Arima, and Mitsuhisa Sato "Evaluation of Power Management Control on the Supercomputer Fugaku" In Proceedings of 2020 IEEE International Conference on Cluster Computing (CLUSTER), EEHPC workshop volume, pp. 484-493, Sep. (2020)
  • Eishi Arima "Classification-Based Unified Cache Replacement via Partitioned Victim Address History" In Proceedings of 2020 23rd Euromicro Conference on Digital System Design (DSD), pp.101-108, Aug. (2020)
  • Eishi Arima, Toshihiro Hanawa, Carsten Trinitis, Martin Schulz "Footprint-Aware Power Capping for Hybrid Memory Based Systems" In Proceedings of the 35th International Conference on High Performance Computing, ISC High Performance (ISC), pp.347--369, Jun. (2020) (acceptance rate: 27/87=31%)
  • Eishi Arima, Martin Schulz "Pattern-Aware Staging for Hybrid Memory Systems" In Proceedings of the 35th International Conference on High Performance Computing, ISC High Performance (ISC), pp.474--495, Jun. (2020) (acceptance rate: 27/87=31%)
  • Eishi Arima, Carsten Trinitis "A Case for Co-scheduling for Hybrid Memory Based Systems" 48th International Conference on Parallel Processing (ICPP), Poster Session, Aug. (2019)
  • Eishi Arima "Optimizations for Computing Systems with Emerging Memory Technologies" The Asia Pacific Society for Computing and Information Technology (APSCIT), Jul. (2019) (invited talk)
  • Eishi Arima, Toshihiro Hanawa, Martin Schulz "Toward Footprint-Aware Power Shifting for Hybrid Memory Based Systems" 47th International Conference on Parallel Processing (ICPP), Poster Session, Aug. (2018)
  • Eishi Arima, Hiroshi Nakamura "Page Table Walk Aware Cache Management for Efficient Big Data Processing" The eighth workshop on Big data benchmarks, Performance Optimization, and Emerging hardware (BPOE-8) (in conjunction with ASPLOS 2017), Apr. (2017)
  • Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita,Takashi Nakada, Hiroshi Nakamura "4Mb STT-MRAM-based Cache with Memory-Access-aware Power Optimization and Novel Write-Verified-Write / Read-Modified-Write Scheme" In Proceedings of 2016 IEEE International Solid-State Circuits Conference (ISSCC), pp.132--133, Feb. (2016) (acceptance rate: 200/595=34%)
  • Susumu Takeda, Hiroki Noguchi, Kumiko Nomura, Shinobu Fujita, Shinobu Miwa, Eishi Arima, Takashi Nakada, Hiroshi Nakamura "Low-power cache memory with state-of-the-art STT-MRAM for high-performance processors" In Proceedings of The 12th International SoC Design Conference (ISOCC), pp.153--154, Nov. (2015)
  • Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura "Immediate Sleep: Reducing Energy Impact of Peripheral Circuits in STT-MRAM Caches" In Proceedings of The 33rd IEEE International Conference on Computer Design (ICCD), pp.149--156, Oct. (2015) (acceptance rate: 83/269=31%)
  • Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura "Subarray Level Power-Gating in STT-MRAM Caches to Mitigate Energy Impact of Peripheral Circuits" 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), Work-in-Progress Session, June (2015)
  • Eishi Arima, Toshiya Komoda, Takashi Nakada, Shinobu Miwa, Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Hiroshi Nakamura "Analyzing Requirements Specification of STT-MRAM Last Level Cache Considering Low CPU Loads" IEICE Transactions, Vol.J97-A, No.10, pp.629-647, (2014) (in Japanese)
  • Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura "Fine-Grain Power-Gating on STT-MRAM Peripheral Circuits with Locality-aware Access Control" The Memory Forum (in conjunction with the 41st International Symposium on Computer Architecture), June (2014)
  • Eishi Arima, Toshiya Komda, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura "Lost Data Prefetching to Reduce Performance Degradation Caused by Powering off Caches" IPSJ Transaction of Advanced Computing Systems, Vol.6, No.3, pp.118-130, (2013) (in Japanese)
  • Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura "D-MRAM Cache: Enhancing Energy Efficiency with 3T-1MTJ DRAM/MRAM Hybrid Memory," In Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.1813--1818, Mar. (2013) (acceptance rate: 206/829=25%)