See TUMonline
Note: The number of participants is not limited. Registration via TUMonline is required. Registration from 18.03. to 04.04.2024 Registration is also possible after the deadline upon request. To this end, please contact klajd.zyla@tum.de.

After participation the student will know the basic concepts of the system level langauge SystemC. He/she will have the ability to build and simulate SystemC models, and to use SystemC for the exploration of different architecture alternatives.

The SystemC Laboratory provides an introduction into the system level language SystemC, which is used to model and simulate digital systems consisting of hardware and software components.The following main aspects are covered: Motivation for SystemC, usage in the design flow, application on different abstraction levels, language elementes of SystemC. Special focus is given to modeling on transaction level (TLM). An application form the area of data communications (IP packet processing) is explored on a HW/SW platform to demonstrate the features and the practical use of SystemC. The exercises are done independently by each participant on Linux workstations using publically available tools.

C or preferably C++ programming skills

At the beginning of the course the theoretical background of SystemC is conveyed in several lectures. The lab exercises are done independently by each student based on a manual with the description of the different experiments. There is no given schedule, the exercises can be done with arbitrary timing. In addition, support to carry out the exercises will be given at specific tutor hours. The lab experiments will be carried out on the EIKON computers.

The final grade is made up of 60% grade of the final exam - written exam, 60 min, no material allowed 40% grade of the two exercises

- T. Grötker, et. al., "System Design with SystemC", Kluwer - D.C. Black, "SystemC: From the Ground Up", Springer