Mannheim EMDRIVE is a BMBF-funded project for the conception and realtime(RT)-compatible extension of central computing platforms and embedded compute networks for future highly automated vehicles. The project network consists of several industry partners from the automotive industry accompanied by partners from academia.
The overall goal of the partners in the course of the project is the development of a hierarchical, scalable platform concept for centralized high performance automotive RT-compute boardnets (Sensor2Edge) and the transfer of results to automotive industry. This can be broken down into the following subgoals within the project:
Embedded RT Compute Performance
Power Consumption
Dynamic, Distributed Computing
RT-Monitoring and Diagnosis
Our Contribution: RT Monitoring and Diagnosis
Modern vehicles already host 100+ Electronic Control Units (ECUs) running more than 100 million lines of code—and software complexity will only grow with autonomous-driving features. Because many sporadic, software-induced faults escape lab testing, vehicles need an in-field mechanism to observe, diagnose, and adapt throughout their lifetime.
Our solution, the Diagnosis Unit (DU), delivers exactly that. Built as a modular HW/SW co-design that can be retro-fitted at a gateway’s mirror port, the DU provides cross-layer, real-time monitoring while remaining virtually invisible to normal in-vehicle operation.
How It Works
Ethernet-Traffic Snooping
The DU taps mirrored traffic on the zonal gateway and applies threshold- and ML-based analytics to detect anomalies such as timing irregularities, message-injection patterns, or traffic-burst deviations.
Microcontroller Trace Analysis
When a network anomaly is flagged, the DU remotely configures the target ECU’s Multi-Core Debug Solution (MCDS) via TAS, records a short execution trace, and analyzes CPU load, control-flow deviations, and timing violations.
Dynamic Anomaly Tree (DAT)
A runtime-reconfigurable tree links communication symptoms to likely processing-level root causes. The backend can update this tree on-the-fly across an entire fleet, turning every car into a collaborative diagnostics sensor.
Edge-to-Cloud Workflow
Heavy data (raw traces) is processed locally on a Zynq UltraScale+ ZCU102 platform (PL for packet parsing, PS for analysis). Only compact summaries—typically a few kB—are uploaded for fleet-wide orchestration and expert review, minimizing bandwidth overhead.
Why It Matters
Reconfigurable & Future-Proof – Cloud-driven updates let the DU adapt to new fault patterns without workshop visits.
Minimal Intrusion – Operates on mirrored Ethernet traffic; no extra latency or bandwidth impact on the IVN.
Comprehensive Coverage – Correlates system-level network symptoms with component-level execution traces, enabling root-cause insight instead of mere symptom reporting.
With its flexible architecture and fleet-coordinated intelligence, the Diagnosis Unit pushes automotive runtime monitoring beyond static OBD routines—empowering engineers to uncover and fix elusive, software-driven faults long after vehicles leave the factory floor.
Current work
Simulation of Zonal In-Vehicle Network Architectures Ongoing development and evaluation of Ethernet-based zonal IVNs using OMNeT++, modeling Time-Sensitive Networking (TSN) behavior and ECU communication flows across mirrored gateway ports.
AI-Based Ethernet Anomaly Detection Implementation of anomaly detection mechanisms using deep learning models such as LSTM autoencoders and Transformer architectures in Python (TensorFlow/Keras). These models aim to identify timing irregularities, unexpected traffic bursts, and ID sequence anomalies in live Ethernet traffic.
AUTOSAR Integration on Infineon AURIX (TC397) Development of diagnostic and control logic on Infineon AURIX TC397 microcontrollers, including AUTOSAR-compliant applications responsible for real-time vehicle sub-functionality (e.g., lane detection, control logic, actuation).
Real-Time Microcontroller Trace Collection via MCDS Leveraging the Multi-Core Debug Solution (MCDS) integrated in the AURIX TC397 to collect fine-grained execution traces. These traces are triggered and retrieved via the Tool Access Socket (TAS) server interface, and subsequently analyzed to detect processing anomalies such as excessive instruction duration, memory misaccesses, or execution flow deviations.
Trace Analysis and Cloud-Coordinated Diagnosis Development of a modular Trace Analyzer hosted on the Zynq UltraScale+ MPSoC, capable of identifying anomalous runtime behavior through timing and control-flow analysis. Diagnostic results are compiled into compact summaries and sent to a centralized cloud backend, which maintains a Dynamic Anomaly Tree (DAT) and orchestrates fleet-wide diagnosis strategies through over-the-air reconfiguration.
FPGA-Accelerated Machine Learning Anomaly Detection for SOME/IP-Based Automotive Ethernet
Description
About the Project Modern in-vehicle networks (IVNs) increasingly rely on Automotive Ethernet as the communication backbone, with SOME/IP serving as the dominant service-oriented protocol for inter-ECU communication. As IVN complexity grows, communication anomalies—arising from software faults, timing failures, or unexpected traffic behaviors—pose challenges to functional safety. Within the EMDRIVE project, our team is developing a Diagnosis Unit (DU) on the Xilinx ZCU102 platform that monitors Automotive Ethernet traffic in real time. The current PL-side implementation relies on static rule-based packet checks, which limits its detection capability against evolving and unseen behaviors.
Project Description The goal of this thesis is to design, implement, and evaluate a machine learning-based anomaly detection module on the Programmable Logic (PL) side of the ZCU102, capable of processing SOME/IP traffic at line rate without dropping packets. The module learns the normal behavior of the network at the flow and header level and flags deviations as anomalies, providing higher detection accuracy and adaptability than the existing rule-based unit. Deep payload semantics are out of scope. The work targets 100BASE-T1, with timing-based scalability analysis toward 1000BASE-T1. The thesis focuses on static-model deployment, where on-line adaptation to behavioral shift is identified as a relevant follow-on direction.
Phase 1 - Foundational (must complete):
Literature study and method selection: Review existing ML-based anomaly detection methods for Automotive Ethernet and select one functionally proven approach (e.g., quantized MLP, autoencoder, or isolation forest) suitable for FPGA deployment.
Anomaly taxonomy: Define a behavioral anomaly taxonomy for SOME/IP traffic covering topological, temporal, volumetric, structural, and semantic deviation classes at flow and header level.
Software baseline and reference behavior: Implement and validate the selected method in Python on a publicly available Automotive Ethernet dataset. Document the rule set of the existing PL-side detector to establish a meaningful comparison baseline.
Quantization and hardware generation: Apply quantization-aware training and generate a synthesizable inference IP using FINN or hls4ml, verify functional correctness in simulation.
Phase 2 - Core (target):
PL integration: Integrate the inference IP with the existing Ethernet parser via AXI4-Stream, implement SOME/IP header parsing and feature extraction in hardware, expose anomaly score and class to the PS via AXI-Lite registers.
On-board evaluation: Measure detection accuracy, false-positive rate, latency, throughput, and resource utilization on the ZCU102 at 100BASE-T1.
Key Responsibilities:
Survey relevant literature and select a single proven detection method as the foundation.
Train, validate, and quantize the model in Python.
Generate, integrate, and verify the FPGA inference IP on the ZCU102.
Evaluate the system end-to-end and document results clearly.
Present intermediate progress in periodic meetings
Prerequisites
Required Skills:
Solid background in digital design and FPGA development; experience with Xilinx Vivado/Vitis.
Working knowledge of Python and a deep learning framework (PyTorch or TensorFlow).
Familiarity with C/C++ and, ideally, High-Level Synthesis (HLS).
Basic understanding of Ethernet, IP, and UDP/TCP networking.
Benefits:
Hands-on experience with the full FPGA-ML co-design flow on automotive-relevant hardware.
Exposure to current research in in-vehicle network dependability within the EMDRIVE project.
Opportunity to contribute to a publishable research direction with potential for a co-authored paper.
Collaborative environment with industry-leading partners.
Comparative Analysis of Local vs. Cloud Processing Approaches
Description
In today’s data-driven world, processing approaches are typically divided between cloud-based solutions—with virtually unlimited resources—and localized processing, which is constrained by hardware limitations. While the cloud offers extensive computational power, localized processing is often required for real-time applications where latency and data security are critical concerns.
To bridge this gap, various algorithms have been developed to pre-process data or extract essential information before it is sent to the cloud.
The goal of this seminar is to explore and compare these algorithms, evaluating their computational load on local hardware and their overall impact on system performance.
Contact
Zafer Attal
zafer.attal@tum.de
Supervisor:
Zafer Attal
Open Work
If you are interested in any of the current work items that are mentioned above and there is currently no open position, please do not hesitate to contact Zafer Attal.
Completed Work
Non-Intrusive Monitoring of Core Utilization on a Multicore Automotive Control Unit (Master Thesis, 2023)
Simulation of Zonal-Architecture Intra-Vehicular Network with TSN Functionality (Teaching Assistant, 2022–2023)
Implementation of a Real-Time Diagnosis Unit Prototype on ZCU102 Designed and implemented a hardware/software co-design on a Zynq UltraScale+ MPSoC (ZCU102), splitting diagnostic tasks between the Programmable Logic (PL) for Ethernet packet parsing and the Processing System (PS) for trace analysis and backend communication.
Integration of Anomaly Detection in Ethernet Traffic Configured the DU to detect specific Ethernet anomalies such as timing deviations, burst inconsistencies, and traffic pattern changes, using empirical thresholds and real traffic profiles.
Aurix ECU Trace Triggering and Retrieval via TAS Connected the DU to Infineon Aurix TC397 boards using TAS to remotely configure, trigger, and retrieve execution traces via the Multi-Core Debug Solution (MCDS).
Demonstration Setup and Validation in a Simulated Function Chain Implemented a testbed with three Aurix boards simulating a Lane Keeping Assistant (LKA). Successfully validated end-to-end detection of communication anomalies, triggering of trace capture, and analysis of processing deviations.
Zafer Attal, Matthias Ernst, Gasper Skvarc, Ibai Irigoyen, Albrecht Mayer, Thomas Wild, Andreas Herkersdorf: An Approach for Automotive ECU Diagnosis via Ethernet Snooping & Microcontroller Tracing. 28th Euromicro Conference Series on Digital System Design (DSD) 2025, 2025 more…
Patrick Schmidt, Iuliia Topko, Matthias Stammler, Tanja Harbaum, Juergen Becker, Rico Berner, Omar Ahmed, Jakub Jagielski, Thomas Seidler, Markus Abel, Marius Kreutzer, Maximilian Kirschner, Victor Pazmino, Robin Sehm, Lukas Groth, Andrija Neskovic, Rolf Meyer, Saleh Mulhem, Mladen Berekovic, Matthias Probst, Manuel Brosch, Georg Sigl, Thomas Wild, Matthias Ernst, Andreas Herkersdorf, Florian Aigner, Stefan Hommes, Sebastian Lauer, Maximilian Seidler, Thomas Raste, Gasper Bozic, Ibai Irigoyen Ceberio, Muhammad Hassan, Albrecht Mayer: EMDRIVE Architecture: Embedded Computing And Diagnostics From Sensor To Edge. DATE 2024 - Design, Automation and Test in Europe Conference, 2024 more…
Gasper Skvarc Bozic, Ibai Irigoyen Ceberio, Matthias Ernst, Albrecht Mayer: A New Generation Automotive Tool Access Architecture for Remote in-Field Diagnosis. WCX SAE World Congress Experience 2023, 2023 more…
