Chip Multicore Processors
| Lecturer (assistant) | |
|---|---|
| Duration | 3 SWS |
| Term | Sommersemester 2026 |
| Language of instruction | English |
Admission information
See TUMonline
Note: Registration via TUMonline
Note: Registration via TUMonline
Description
The lecture starts with the motivation for chip multicore processors. Starting from the technological background, the potential and challenges of parallel execution are discussed and state-of-the-art processors will be presented to classify multicore processors. A central aspect of chip multicore processors is the memory hierarchy. With the introduction of caches the coherency problem arises. Solutions for this problem are discussed during the lecture. The implementation of synchronization, both from the hardware and the software view, are discussed subsequently. Non-blocking data structures and Transactional Memory are introduced as possible solutions to relax the synchronization problem. The on-chip interconnect, and especially Network-on-Chip (NoC) are discussed in detail as part of the lecture. Finally, programing models and implementation challenges are discussed.
Prerequisites
Basic understanding of computer architectures. Ideally the lecture 'System-on-Chip Technologies'.
Teaching and learning methods
The basic learning method is presentation during the lecture, supplemented with group discussions. During the tutorial examples will be discussed. For a better understanding students will read scientific publications as self studies. Case studies will be discussed to get a practical understanding of chip multicore processors.