Marco Liess, M.Sc.

Research Associate 

Technical University of Munich
TUM School of Computation, Information and Technology
Chair of Integrated Systems
Arcisstr. 21
80333 München
Germany

Tel.: +49.89.289.23873
Fax: +49.89.289.28323
Gebäude: N1 (Theresienstr. 90)
Raum: N2139
Email: marco.liess@tum.de

Curriculum Vitae

  • 2022 - today: PhD student at LIS, TU Munich
  • 2019 - 2021: Master of Science in Electrical and Computer Engineering at TU Munich
    • Major: Embedded and Control Systems
    • Working Student on Microcontroller Security at the Fraunhofer Institute for Applied and Integrated Security (AISEC)
    • Thesis: "Frame Synchronization for Satellite-based IoT Applications" at the German Aerospace Center (DLR)
  • 2016 - 2019: Bachelor of Science in Electrical and Computer Engineering at TU Munich
    • Focus on Computer Networks, Embedded Systems and Security
    • Thesis: "Efficient Key Establishment for IoT Applications" at Fraunhofer (AISEC)

Research Interests

I am researching on hardware aspects of network interfaces and the attached processing resources. This includes the acceleration of the data paths from network interface to processor, the mitigation of memory bottlenecks, dynamic power management, efficient hash algorithms and lookup mechanisms and much more.

Teaching

 

Chip Multicore Processors (since SS 2024)

(Seminar Integrierte Systeme WS 2022/23 until WS2023/24)

(Seminar on Topics in Integrated Systems WS 2022/23 until WS2023/24)

Offered Work

If I'm currently not offering any work or the topics are not what you're looking for, feel free to contact me directly anyways!

Implementation and Evaulation of Hardware Match-Action Tables on FPGA

Description

With the advent of research on the next generation of
mobile communications 6G, we are engaged in exploring
architecture extensions for Smart Network Interface Cards
(SmartNICs). To enable adaptive, energy-efficient and
low-latency network interfaces, we are prototyping a
custom packet processing pipeline on FPGA-based NICs,
partially based on the open-nic project
(https://github.com/Xilinx/open-nic).

Incoming packet flows should be differentiated and differently
processed, which is typically solved with match-action tables (MATs).
MATs match on a certain packet condition (e.g. packet header 5-tuple) and execute an according action (e.g. dropping, forwarding or modifying the packet). A recent Xilinx IP core implements MATs that can be programmed with P4, a programmable packet processing language gaining momentum in networking. The goal of this work is to investigate the implementation of MATs in hardware, integrate them into our current HDL design based on open-nic and test and evaluate the results.

Prerequisites

  •     Programming skills in VHDL/Verilog and C (and Python)
  •     Practical experience with FPGA Design and Implementation
  •     Good Knowledge of computer networks, OSI layer model and protocols
  •     Preferably basic knowledge of P4 packet processing language

Contact

Marco Liess, M. Sc.

Tel.: +49.89.289.23873
Raum:
N2139
Email:
marco.liess@tum.de

Supervisor:

Marco Liess

Ongoing Work

An Overview of Service Migration in Modern Edge Computer Networks

Description

In modern Edge computer networks, applications and services should adhere to service-level agreements (SLA) like low latency or minimal throughput. Depending on demand and resource availability, these services have to be migrated between compute nodes to ensure these SLAs.

Service migration is a critical aspect of Edge computing, enabling the movement of services closer to the data source or end-users for improved performance and reduced latency. However, it comes with its own set of challenges, such as maintaining service continuity and managing resource constraints. This involves checkpointing and restarting of the applications (potentially in containers), as well as moving the data from one compute node to the other. This data movement could be further improved with RDMA technology.

This seminar should provide a background overview of the required technologies for service migration and explore recent improvements for low-latency service migration in both hardware and software.

Contact

marco.liess@tum.de

Supervisor:

Marco Liess

Exploring Linux eBPF Mechanism for SmartNICs

Description

eBPF (extended Berkeley Packet Filter) is a technology used in Linux for running user-defined sandboxed programs in the kernel without changing kernel source code or loading kernel modules. In networking, eBPF can be used to redefine the network stack behavior by allowing the dynamic insertion of powerful networking and security functions deep inside the Linux kernel.

SmartNICs (Network Interface Cards with a programmable processor) can offload some processing tasks that the system CPU would normally handle. This is beneficial in freeing up CPU resources and improving networking performance. eBPF can be used in conjunction with SmartNICs to offload some network processing tasks to the SmartNIC, further enhancing performance.

The goal of this seminar topic is to provide a background overview of Linux eBPF in networking and to explore how eBPF can be leveraged in SmartNICs to improve network performance and security. Look into recent advancements, challenges, and future prospects.

Contact

marco.liess@tum.de

Supervisor:

Marco Liess

Hardware Interrupt Generation for Smart Servers

Description

With the advent of research on the next generation of
mobile communications 6G, we are engaged in exploring
architecture extensions for Smart Network Interface Cards
(SmartNICs). To enable adaptive, energy-efficient and
low-latency network interfaces, we are prototyping a
custom packet processing pipeline on FPGA-based NICs,
partially based on the open-nic project
(https://github.com/Xilinx/open-nic).

To improve the performance and energy efficiency of a
modern server, SmartNICs can be used to preprocess
incoming packets and gather characteristics on traffic and processing requirements. This information can be used to change the processing behavior of the server and react to the dynamic network and processing requirements. To do so, the server has to be notified of detected events using an interrupt.

The goal of this work is to implement hardware-based interrupt generation in an FPGA-based SmartNIC using HDL and PCIe IP cores, registering the interrupt with the Linux interrupt driver as well as writing a suitable ISR (interrupt service routine). This mechanism should be functionally verified in a hardware testbed and evaluated regarding the latency of the interrupt. Additionally, the work could be extended to include setting the core affinity of an interrupt and generating interrupts destined for specific CPU cores.

Prerequisites

  • Programming skills in VHDL/Verilog and C (and Python)
  • Practical experience with FPGA Design and Implementation
  • Good Knowledge of computer architecture and low-level software / drivers
  • Comfortable with the Linux command line and bash

Contact

Marco Liess, M. Sc.

Tel.: +49.89.289.23873
Raum:
N2139
Email:
marco.liess@tum.de

Supervisor:

Marco Liess

Webserver Setup for Benchmarking of a SmartNIC-assisted Server

Description

With the advent of research on the next generation of
mobile communications 6G, we are engaged in exploring
architecture extensions for Smart Network Interface Cards
(SmartNICs). To enable adaptive, energy-efficient and
low-latency network interfaces, we are prototyping a
custom packet processing pipeline on FPGA-based NICs,
partially based on the open-nic project
(https://github.com/Xilinx/open-nic).

To properly evaluate the performance of a
SmartNIC-assisted server, a webserver-based application
shall be setup in a Linux OS environment and tested with different request rates. Additionally, the performance of single- vs. multicore platforms for one and multiple webserver instances should be compared. CPU core isolation mechanisms can be used to setup such scenarios on the server.

The goal of this work is to setup a webserver (e.g. NGINX), potentially with a database backend (e.g. MongoDB) and develop a measurement and testing methodology for performance benchmarking of a SmartNIC-assisted server. This includes throughput and latency measurements, as well as analysis of the CPU and network utilization.

Prerequisites

  •     Programming skills C and Python
  •     Good Knowledge of computer networks, OSI layer model and protocols
  •     Comfortable with the Linux command line and bash
  •     Preferably experience with Linux drivers and low-level software

Contact

Marco Liess, M. Sc.

Tel.: +49.89.289.23873
Raum:
N2139
Email:
marco.liess@tum.de

Supervisor:

Marco Liess

Hardware Queue-to-Core Pinning for Load Balancing using SmartNICs

Description

With the advent of research on the next generation of
mobile communications 6G, we are engaged in exploring
architecture extensions for Smart Network Interface Cards
(SmartNICs). To enable adaptive, energy-efficient and
low-latency network interfaces, we are prototyping a
custom packet processing pipeline on FPGA-based NICs,
partially based on the open-nic project
(https://github.com/Xilinx/open-nic).

Load balancing is a challenging task in modern data
centers and servers, as the number of processing cores rises (96 cores in recent AMD Epyc platforms) and the packet processing workload should be distributed equally among them. To assist this process, incoming packet flows should be differentiated and assigned to different queues already in the NIC hardware. These queues must then be pinned to different processor cores to ensure the hardware load-balancing algorithm works correctly.

The goal of this work is to implement the queue assignment in the FPGA SmartNIC platform using HDL, configuring the NIC driver to use the correct queues, and pinning the processing of the queues onto different CPU cores. Further, functional verification as well as performance evaluation should be done on the system.

Prerequisites

  •     Programming skills in VHDL/Verilog and C (and Python)
  •     Practical experience with FPGA Design and Implementation
  •     Good Knowledge of computer networks, OSI layer model and protocols
  •     Comfortable with the Linux command line and bash

Contact

Marco Liess, M. Sc.

Tel.: +49.89.289.23873
Raum:
N2139
Email:
marco.liess@tum.de

Supervisor:

Marco Liess

Multicore-Optimierung eines bildverarbeitenden Systems

Description

Im industriellen Umfeld werden Informationen zunehmend in visuellen Codes (z.B.
Strichcodes, QR-Codes) zur automatisierten Verarbeitung abgelegt. Steigende
Durchsatzzahlen stellen immer höhere Anforderungen an die Geschwindigkeit der
Datenverarbeitung.
In dieser Arbeit soll anhand eines kostengünstigen kommerziell erhältlichen Multicore-
Systems untersucht werden, inwieweit bisher durch Hardware realisierte
Verarbeitungsgeschwindigkeiten durch Parallelisierung der Auswertungsschritte in CPU-Systemen erreicht, werden können.
Insbesondere soll untersucht werden, ob spezialisierte Co-Prozessoren (z. B. Vector
Processing Units (VPUs)) zur Beschleunigung beitragen können oder wie diese auf die Aufgabe hin optimiert gestaltet werden können (Application-Specific Instructionset
Processor (ASIP)).

Supervisor:

Marco Liess

A Deep Dive into C-States, Idle Governors and the Prospects of an eBPF Idle Governor

Description

Linux is one of the most utilized Operating Systems in Embedded Systems and Cloud
Infrastructure worldwide. Sustainability will become more relevant in the future and saving power is a crucial aspect. This shows the increasing importance of efficient Linux Power Management.


The Power Management in Linux is implemented in several kernel subsystems correlating to hardware characteristics, like P-States (Frequency Scaling) and C-States (Sleep States). This thesis examines the Idle Power Management of Linux, and therefore focuses on C-States. C-States are per Core states and allow parts of the core to shut down individual features. Each processor implements C-States in different ways. Increasing C-State number, e.g. C6, translate to a deeper sleep with lower energy consumption and higher power-on reaction time.


The recently released eBPF functionality makes the kernel more programmable, bypassing the original monolithic characteristics. This mechanism can be divided into four components: the eBPF hooks in the kernel, the interfaces, the in-kernel eBPF infrastructure to execute eBPF bytecode and compile into native code and verify the code and finally the eBPF application itself, which can be written in a C like dialect and compiled into eBPF bytecode by LLVM and GCC.


This thesis aims to analyze and compare the idle governors in the current Kernel in specific situations. It also should provide insight in the C-State usage depending on the architecture. The data is acquired using specific Tracepoints within the Kernel, which can be recorded and parsed with the Kernel Tool perf. Furthermore, we explore the feasibility of a custom eBPF powered idle governor.

Supervisor:

Marco Liess - Hagen Pfeifer (Rohde & Schwarz)

SmartNIC Enhancements for Network Node Resilience

Description

The Chair of Integrated Systems participates in the DFG Priority Program “Resilient Connected
Worlds” by the German Research Foundation (SPP 2378). Our goal is to investigate which resilience
functions, that conventionally are provisioned by the central compute resources of Internet
Networking or Compute Nodes, can meaningfully be migrated onto the Network Interface Card (NIC).
By inspecting packet streams at full line rate (10 – 40 Gbps) a set of resilience functions, such as
access shields against a known set of traffic flows or redundant flow processing for a selected and
configured number of flows, shall be offloaded from centralized compute resources and offered in a
more performant and energy-efficient manner. Flows are identified by their so-called 5-tuple
consisting of source-/destination IP addresses and transport protocol ports as well as the protocol
field of the IP packet header.
During the Bachelor/Master Thesis, you will develop VHDL code for realizing one or more of the
SmartNIC Resilience building blocks: 5 tuple address matching against a preconfigured set of
addresses, perform the packet duplication for delivery to different processor cores or threads,
investigate methods to flexibly perform the address match on the entire or a variable subsection of
the 5 tuple array.

Prerequisites

  • VHDL coding, synthesis and FPGA prototyping
  • Braodband communication or Internet Networking Technologies,
    in particular OSI Layer packet header formats
  • Digital circuit design

Contact

Marco Liess
Room N2139
Tel. 089 289 23873
marco.liess@tum.de

Supervisor:

Marco Liess

Publications

  • Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf: FlexRoute: A Fast, Flexible and Priority-Aware Packet-Processing Design. 32nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP 2024), 2024 more… BibTeX Full text ( DOI )
  • Marco Liess, Julian Demicoli, Tobias Tiedje, Matthias Lohrmann, Matthias Nickel, Marco Luniak, Dimitris Prousalis, Thomas Wild, Ronald Tetzlaff, Diana Göhringer, Christian Mayr, Karlheinz Bock, Sebastian Steinhorst, Andreas Herkersdorf: X-MAPE: Extending 6G-connected Self-adaptive Systems with Reflexive Actions. 2023 IEEE Conference on Network Function Virtualization and Software Defined Networks (NFV-SDN), 2023 more… BibTeX
  • Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf: FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance SmartNICs. 31st IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2023), 2023 more… BibTeX Full text ( DOI )
  • Marco Liess, Francisco Lázaro, Andrea Munari: Frame Synchronization Algorithms for Satellite Internet of Things Scenarios. 2022 11th Advanced Satellite Multimedia Systems Conference and the 17th Signal Processing for Space Communications Workshop (ASMS/SPSC), 2022 more… BibTeX Full text ( DOI )