Marco Liess, M.Sc.

This seminar should explore innovations in optical interconnects using silicon photonics.

The incoming traffic load and with it the computing requirements on network processing nodes such as edge servers can span multiple magnitudes in a matter of milliseconds and less. The systems are ususally dimensioned to cope with peak loads, resulting in a low resource utilization when traffic is little. To ensure a highly energy-efficient resource utilization, dynamic power management with respect to fluctuating processing requirements is necessary to reduce the power consumption (e.g. by dynamic voltage frequency scaling (DVFS) or power gating) in times of low traffic load.

The goal of this seminar is to establish an overview on current approaches for power management in network processing nodes such as edge servers. Hereby, the focus lies on the employed methods, the timescales with which they operate and their impact on processing performance indicators such as throughput and latency.

A starting point for the literature research can be:
https://dl.acm.org/doi/pdf/10.1145/3466752.3480098

With the advent of research on the next generation of
mobile communications 6G, we are engaged in exploring
architecture extensions for Smart Network Interface Cards
(SmartNICs). To enable adaptive, energy-efficient and
low-latency network interfaces, we are prototyping a
custom packet processing pipeline on FPGA-based NICs,
partially based on the open-nic project
(https://github.com/Xilinx/open-nic).

Incoming packet flows should be differentiated and differently
processed, which is typically solved with match-action tables (MATs).
MATs match on a certain packet condition (e.g. packet header 5-tuple) and execute an according action (e.g. dropping, forwarding or modifying the packet). A recent Xilinx IP core implements MATs that can be programmed with P4, a programmable packet processing language gaining momentum in networking. The goal of this work is to investigate the implementation of MATs in hardware, integrate them into our current HDL design based on open-nic and test and evaluate the results.

• Programming skills in VHDL/Verilog and C (and Python)
• Practical experience with FPGA Design and Implementation
• Good Knowledge of computer networks, OSI layer model and protocols
• Preferably basic knowledge of P4 packet processing language

With the advent of research on the next generation of mobile communications 6G, LIS is engaged in exploring architectures and architecture extensions for networking hardware. In order to research on energy-efficient and low-latency network interfaces for next-generation networks, we are setting up a hardware testbed with FPGA-based Network Interface Accelerator Cards and AMD Epyc and Ryzen Processors.

The incoming traffic load and with it the computing requirements on network processing nodes such as edge servers can span multiple magnitudes in a matter of milliseconds and less. The systems are ususally dimensioned to cope with peak loads, resulting in a low resource utilization when traffic is little. To ensure a highly energy-efficient resource utilization, dynamic power management with respect to fluctuating processing requirements is necessary to reduce the power consumption (e.g. by dynamic voltage frequency scaling (DVFS) or power gating) in times of low traffic load.

The goal of this work is to explore Linux power management possibilities on AMD processors. This involves researching possible power management options (e.g. DVFS) in Linux, understanding and using the provided API, verifying the correct functionality and setting up a framework for measurement and benchmarking. The measurements shall be processed and evaluated concerning key performance indicators like power consumption, switching delay, etc.

• Good experience with Linux, Command Line Tools and Bash scripting
• Programming skills in C and Python
• Preferably practical experience with the Linux Kernel, Kernel tracing functionality and low-level software
• Solid understanding of operating system concepts and hardware/software interactions

With the advent of research on the next generation of
mobile communications 6G, LIS is engaged in exploring
architectures and architecture extensions for networking
hardware. In order to research on energy-efficient and
low-latency network interfaces for next-generation
networks, we are setting up a hardware testbed with
FPGA-based Network Interface Accelerator Cards in the
form of Xilinx Alveo and NetFPGA SUME FPGA boards.
This requires the bring-up and evaluation of the  HDL
Design, the Linux kernel drivers and applications.

OpenNIC provides open-source code for an HDL design and kernel driver as basis for a custom hardware network interface on FPGAs. The goal of this work is to setup the Linux DPDK driver to interface with the HDL design on the FPGA, validate the communication with the FPGA and correct functionality of the driver and finally evaluate the driver, especially with comparison to the standard Linux network driver. This can involve establishing a test setup with additional postprocessing regarding key performance indicators (KPIs) such as latency, bandwidth, memory footprint, etc., and tracing of the drivers and Linux network stack.

- Good experience with Linux, Command Line Tools and Bash scripting
- Programming skills in C and Python (and VHDL)
- Knowledge of Internet Networking Technologies, in particular OSI layer protocols

The Chair of Integrated Systems participates in the DFG Priority Program “Resilient Connected
Worlds” by the German Research Foundation (SPP 2378). Our goal is to investigate which resilience
functions, that conventionally are provisioned by the central compute resources of Internet
Networking or Compute Nodes, can meaningfully be migrated onto the Network Interface Card (NIC).
By inspecting packet streams at full line rate (10 – 40 Gbps) a set of resilience functions, such as
access shields against a known set of traffic flows or redundant flow processing for a selected and
configured number of flows, shall be offloaded from centralized compute resources and offered in a
more performant and energy-efficient manner. Flows are identified by their so-called 5-tuple
consisting of source-/destination IP addresses and transport protocol ports as well as the protocol
field of the IP packet header.
During the Bachelor/Master Thesis, you will develop VHDL code for realizing one or more of the
SmartNIC Resilience building blocks: 5 tuple address matching against a preconfigured set of
addresses, perform the packet duplication for delivery to different processor cores or threads,
investigate methods to flexibly perform the address match on the entire or a variable subsection of
the 5 tuple array.

• VHDL coding, synthesis and FPGA prototyping
• Braodband communication or Internet Networking Technologies,
  in particular OSI Layer packet header formats
• Digital circuit design

The incoming traffic load and with it the computing requirements on network processing nodes such as edge servers can span multiple magnitudes in a matter of milliseconds and less. The systems are ususally dimensioned to cope with peak loads, resulting in a low resource utilization when traffic is little. To ensure a highly energy-efficient resource utilization, dynamic power management with respect to fluctuating processing requirements is necessary to reduce the power consumption (e.g. by dynamic voltage frequency scaling (DVFS) or power gating) in times of low traffic load.

The goal of this seminar is to establish an overview on current approaches for power management in network processing nodes such as edge servers. Hereby, the focus lies on the employed methods, the timescales with which they operate and their impact on processing performance indicators such as throughput and latency.

A starting point for the literature research can be:
https://dl.acm.org/doi/pdf/10.1145/3466752.3480098

In order to research on energy-efficient and
low-latency network nodes for next-generation
networks, we are setting up a hardware testbed
with FPGA-based Network Interface Accelerator
Cards in the form of Xilinx Alveo FPGA boards.
Previous research in the area of Network Interface
Cards (NICs) at our chair led to HDL Designs of
Packet Processing Pipelines on older generation
FPGAs, which shall serve as basis for further
research on Xilinx Alveo FPGA boards.

Therefore, the goal of this work is to port these existing HDL Designs to the new FPGAs. This includes analyzing the existing designs, extracting the required logic and integrating it into the OpenNIC framework. Further, the functionality of the designs has to be verified by testing.

- Experience with Linux, Command Line Tools and Bash scripting
- Programming skills in VHDL/Verilog and C (and Python)
- Experience with FPGA Design and Implementation