Oliver Lenke, M.Sc.

Research Associate

Technical University of Munich
TUM School of Computation, Information and Technology
Chair of Integrated Systems
Arcisstr. 21
80333 München
Germany

Tel.: +49.89.289.28387
Fax: +49.89.289.28323
Gebäude: N1 (Theresienstr. 90)
Raum: N2114
Email: o.lenke@tum.de

Curriculum Vitae

  • Since 2020 Doctoral Candidate at LIS
  • 2018-2020 Working Student at LIS
  • 2018-2020 Master EI (TUM)
  • 2015-2018 Bachelor EI (TUM)
  • 2016-2019 Student Tutor for Werkstoffe der Elektrotechnik, Regelungssysteme, ...

Offered Work

Fine granular Page Preloading Mechanism on an FPGA Prototype

Keywords:
VHDL, C Programming, Distributed Memory, Data Migration, Task Migration, Hardware Accelerator

Description

Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density make DRAM omnipresend in most computer architectures. However, DRAM accesses are rather slow and require a dedicated DRAM controller
that coordinates the read and write accesses to the DRAM as well as the refresh cycles. In order to reduce the DRAM access latency, memory prefetching is a common technique to access data prior to their actual usage. However, this requires sophisticated prediction algorithms in order to prefetch the right data at the right time.


The Goal of this thesis is to refine an existing DRAM preloading mechanism on an  FPGA based prototype platform. Instead of preloading a whole memory page in a single atomic operation, the refinement should lead to a fine-granular page preloading, i.e. loading multiple small fractions of a page step by step while allowing regular memory accesses to be prioritized intermediately.


Towards this goal, you'll complete the following tasks:
1. Understanding the existing Memory Access and Preloading mechanism
2. VHDL implementation of the refined preloading functionalities
3. Write and execute small baremetal test programs
4. Analyse and discuss the performance results

Prerequisites

  • Good Knowledge about MPSoCs
  • Good VHDL skills
  • Good C programming skills
  • High motivation
  • Self-responsible workstyle

Contact

Oliver Lenke

o.lenke@tum.de

Supervisor:

Oliver Lenke

Ongoing Work

Completed Theses

Interrupt Latency Investigations with YoctoRT and FreeRTOS on Xilinx Versal Evaluation Board
Master's Thesis, Jiawen Qi, April 2024, Cooperation with Rohde&Schwarz

SystemC Model for Memory Preloading
Research Practice, Ali Emre Heybeli, February 2024

An Efficient, Scalable and SIMD-friendly Hybrid FFT Computation Method
Master's Thesis, Jiawen Qi, January 2024, Cooperation with Huawei

SystemC Model for Memory Preloading
Research Practice, Jingyi Liu, December 2023

Lifetime Analysis of Flash Memory Devices in Automotive Use Cases
Bachelor's Thesis, Simon Weigl, July 2023, Cooperation with BMW AG

Automatic Hardening of Registers in Safety Critical Microcontrollers
Bachelor's Thesis, Jonathan Ross, July 2023, Cooperation with Infineon AG

Design and Implementation of a flexible SPI Fault Injection Unit
Bachelor's Thesis, Hannes Matheis, December 2022, Cooperation with Infineon AG

Design and Implementation of a Hardware Accelerator for VSM Page Writeback
Master's Thesis, Thomas Leyk, November 2022, Cooperation with FAU

Scalability Analysis of Hardware Acceleration on Central and Distributed Memory Systems
Master's Thesis, Jens Nöpel, November 2022

Measurement and Analysis of a Tile-based MPSoC System
Research Practice, Gabriel Pempel, November 2022, Cooperation with FAU

Design and Implementation of a HW-based Memory Protection Unit for Tile-based MPSoCs
Master's Thesis, Peter Körner, October 2022, Cooperation with FAU

DYNAMIT: Dynamic Acceleration of Memory-Stores in Tile-based Architectures
Master's Thesis, Michael Geier, August 2022

Laufzeit Vorhersage von Hardwarebeschleuniger und Near-Memory-Computing
Bachelor's Thesis, Sahil Salotra, September 2021

Extending an Utilization Counter Framework for On-Chip AHB Bus Systems
Bachelor's Thesis, Humayra Jeba Binte Mohd Habibur Rahman, July 2021, Cooperation with SIT
Best Thesis Award

Utilization Monitoring and Analysis of a Near-Memory-Computing System
Research Practice, Richard Petri, May 2021

Publications

2023

  • Nora Sperling, Alex Bendrick, Dominik Stöhrmann, Rolf Ernst, Bryan Donyanavard, Florian Maurer, Oliver Lenke, Anmol Surhonne, Andreas Herkersdorf, Walaa Amer, Caio Batista de Melo, Ping-Xiang Chen, Quang Anh Hoang, Rachid Karami, Biswadip Maity, Paul Nikolian, Mariam Rakka, Dongjoo Seo, Saehanseul Yi, Minjun Seo, Nikil Dutt, Fadi Kurdahi: Information Processing Factory 2.0 - Self-awareness for Autonomous Collaborative Systems. DATE 2023, 2023 more… BibTeX Full text ( DOI )

2022

  • Jürgen Becker, Andreas Herkersdorf, Nidhi Anantharajaiah, Oliver Lenke, Akshay Srivatsa, Thomas Wild: Invasive NoCs and Memory Hierarchies for Run-Time Adaptive MPSoCs. In: Invasive Computing. FAU University Press, Universitätsstraße 4, 91054 Erlangen, 2022 more… BibTeX Full text ( DOI )
  • Jürgen Becker, Frank Hannig, Thomas Wild, Marcel Brand, Oliver Lenke, Fabian Lesniak: Validation and Demonstrator. In: Invasive Computing. FAU University Press, Universitätsstraße 4, 91054 Erlangen, 2022 more… BibTeX

2021

  • Oliver Lenke, Richard Petri, Thomas Wild, Andreas Herkersdorf: PEPERONI: Pre-Estimating the Performance of Near-Memory Integration. MEMSYS'21: The International Symposium on Memory Systems, 2021 more… BibTeX
  • Sven Rheindt, Akshay Srivatsa, Oliver Lenke, Lars Nolte, Thomas Wild, Andreas Herkersdorf: Tackling the MPSoC Data Locality Challenge – Part 2 / Chapter 5. In: Multi-Processor System-on-Chip 1. Wiley Online Library, 2021, 87-114 more… BibTeX

2020

  • Sven Rheindt, Andreas Fried, Oliver Lenke, Lars Nolte, Temur Sabirov, Tim Twardzik, Thomas Wild, Andreas Herkersdorf: X-CEL: A Method to Estimate Near-Memory Acceleration Potential in Tile-based MPSoCs. ARCS 2020 - 33rd International Conference on Architecture of Computing Systems, 2020 more… BibTeX
  • Sven Rheindt, Sebastian Maier, Nora Pohle, Lars Nolte, Oliver Lenke, Florian Schmaus, Thomas Wild, Wolfgang Schröder-Preikschat, Andreas Herkersdorf: DySHARQ: Dynamic Software-Defined Hardware-Managed Queues for Tile-Based Architectures. International Journal of Parallel Programming, 2020 more… BibTeX Full text ( DOI )
  • Sven Rheindt, Temur Sabirov, Oliver Lenke, Thomas Wild, Andreas Herkersdorf: X-Centric: A Survey on Compute-, Memory- and Application-Centric Computer Architectures. MEMSYS'20: The International Symposium on Memory Systems , 2020 more… BibTeX

2019

  • Sven Rheindt, Andreas Fried, Oliver Lenke, Lars Nolte, Thomas Wild, Andreas Herkersdorf: NEMESYS: Near-Memory Graph Copy Enhanced System-Software. MEMSYS 19: The International Symposium on Memory Systems, 2019 more… BibTeX