Motivation & Overview

In today's interconnected world, reliable high-performance transaction and smart contract systems are becoming increasingly important due to potentially distrustful stakeholders. The ACE-SUPPRA project is conducting Security, Usability, Performance, and Privacy Research on the Algorand protocol, a promising platform for future blockchain systems due to its Proof-of-Stake (PoS)-based design and powerful smart contract language. ACE-SUPPRA is addressing various challenges of upcoming blockchain networks and investivating new concepts and possibilities to improve the properties implied by its name. Funded by the Algorand Foundation, it is part of the Algorand Centers of Excellence (ACE) program, and encompasses five chairs at TUM, jointly working on the project.

  • Chair of Network Architectures and Services (NET) of Prof. Dr.-Ing. Georg Carle
  • Chair of Integrated Systems (LIS) of Prof. Dr. sc. techn. Andreas Herkersdorf
  • Chair for Software and Systems Engineering (SSE) of Prof. Dr. Alexander Pretschner
  • Chair for Software Engineering for Business Information Systems (SEBIS), of Prof. Dr. Florian Matthes
  • Chair for Strategy and Organization (SAO) of Prof. Dr. Isabell Welpe

Research Focus

At LIS, we are focussing on the development and the evaluation of performance enhancements by increasing the throughput and reducing the latency in the system. Our approach to achive these goals is the development of new SmartNIC solutions to which certain operations can be offloaded. The performance and scalability of the Algorand protocol to a large extent depend on the message processing and forwarding capabilities of relay nodes which we aim to improve using SmartNIC-based hardware accelerators.

Involved Researchers

Franz Biersack

Student Work


Implementation of a SmartNIC-based HW Accelerator for Algorand Relay Nodes to broadcast Blockchain Messages


The Algorand protocol is an environmentally friendly Blockchain technology based on the Proof-of-Stake (POS) consensus mechanism. It represents a new platform for smart contracts trying to solve the blockchain trilemma consisting of scalability, decentralization and security. As part of the ACE-SUPPRA project (Security, Usability, Performance, and Privacy Research in Algorand) we are investigating ways to accelerate the forwarding and broadcasting of Algorand messages throughout the blockchain network with the help of SmartNIC-based HW accelerators to increase the achievable transmission throughput and decrease latencies as well as power consumption.

To this end, the goal of this master thesis is to develop an extension of an existing packet reception, forwarding and delivery SmartNIC design to detect and relay Algorand transaction, block proposal, voting and consensus messages to a given set of network peers. The implementation will require an Algorand message detection entity consisting of a modified packet header parser and a Match-Action-Table. Furthermore, a PCIe-based configuration module for communicating with an attached host PC will be necessary to receive updates on new TCP connections and the IP addresses of the current peer list. The design will also encompass a high priority and bulk broadcast queue for Algorand messages alongside a suitable egress scheduler as well as a message memory and broadcast module for the transmission to four connected peers. Finally, a Packetizer unit will have to be designed, assembling TCP/IP packets and Algorand messages out of multiple Ethernet frames after reception, and vice versa also splitting messages into individual Layer 2 frames prior to their transmission.

Towards this goal you will complete the following tasks:
•    Research existing methods for relaying and broadcasting blockchain messages
•    Implement the design on the NetFPGA-SUME or AMD Alveo U55C prototyping platform
•    Compare and evaluate the implementation with the SW-based Golang implementation of Algorand
•    Document your work in a written thesis report and present your work in a presentation


To successfully complete this project, you should already have the following skills and experiences.
•    Project Laboratory IC-Design or equivalent course
•    Good knowledge about Verilog or VHDL
•    Xilinx Vivado Design Suite and Synopsys VCS / Mentor Graphics ModelSim (tools will be provided)
•    Self-motivated and structured work style


Interested? Questions? Do not hesitate to contact me!

Franz Biersack
Chair of Integrated Systems
Arcisstraße 21, 80333 Munich
Tel. +49 89 289 23869


Franz Biersack