Zafer Attal, M.Sc.

About the Project
Modern in-vehicle networks (IVNs) increasingly rely on Automotive Ethernet as the communication backbone, with SOME/IP serving as the dominant service-oriented protocol for inter-ECU communication. As IVN complexity grows, communication anomalies—arising from software faults, timing failures, or unexpected traffic behaviors—pose challenges to functional safety. Within the EMDRIVE project, our team is developing a Diagnosis Unit (DU) on the Xilinx ZCU102 platform that monitors Automotive Ethernet traffic in real time. The current PL-side implementation relies on static rule-based packet checks, which limits its detection capability against evolving and unseen behaviors.

Project Description
The goal of this thesis is to design, implement, and evaluate a machine learning-based anomaly detection module on the Programmable Logic (PL) side of the ZCU102, capable of processing SOME/IP traffic at line rate without dropping packets. The module learns the normal behavior of the network at the flow and header level and flags deviations as anomalies, providing higher detection accuracy and adaptability than the existing rule-based unit. Deep payload semantics are out of scope. The work targets 100BASE-T1, with timing-based scalability analysis toward 1000BASE-T1. The thesis focuses on static-model deployment, where on-line adaptation to behavioral shift is identified as a relevant follow-on direction. 

Phase 1 - Foundational (must complete):

• Literature study and method selection: Review existing ML-based anomaly detection methods for Automotive Ethernet and select one functionally proven approach (e.g., quantized MLP, autoencoder, or isolation forest) suitable for FPGA deployment.
• Anomaly taxonomy: Define a behavioral anomaly taxonomy for SOME/IP traffic covering topological, temporal, volumetric, structural, and semantic deviation classes at flow and header level.
• Software baseline and reference behavior: Implement and validate the selected method in Python on a publicly available Automotive Ethernet dataset. Document the rule set of the existing PL-side detector to establish a meaningful comparison baseline.
• Quantization and hardware generation: Apply quantization-aware training and generate a synthesizable inference IP using FINN or hls4ml, verify functional correctness in simulation.

Phase 2 - Core (target):

• PL integration: Integrate the inference IP with the existing Ethernet parser via AXI4-Stream, implement SOME/IP header parsing and feature extraction in hardware, expose anomaly score and class to the PS via AXI-Lite registers.
• On-board evaluation: Measure detection accuracy, false-positive rate, latency, throughput, and resource utilization on the ZCU102 at 100BASE-T1. 

Key Responsibilities: 

• Survey relevant literature and select a single proven detection method as the foundation.
• Train, validate, and quantize the model in Python.
• Generate, integrate, and verify the FPGA inference IP on the ZCU102.
• Evaluate the system end-to-end and document results clearly.
• Present intermediate progress in periodic meetings

Prerequisites

In today’s data-driven world, processing approaches are typically divided between cloud-based solutions—with virtually unlimited resources—and localized processing, which is constrained by hardware limitations. While the cloud offers extensive computational power, localized processing is often required for real-time applications where latency and data security are critical concerns.

To bridge this gap, various algorithms have been developed to pre-process data or extract essential information before it is sent to the cloud.

The goal of this seminar is to explore and compare these algorithms, evaluating their computational load on local hardware and their overall impact on system performance.