Lars Nolte, M.Sc.

Research

Information about my research area can be found on the PASSTA project page.

Thesis Offers

Interested in an internship or a thesis? Please send me an email.
The given type of work is just a guideline and could be changed if needed.
From time to time, there might be some work, that is not announced yet. Feel free to ask!

Ongoing Thesis

Hardware-Accelerated Linux Kernel Tracing

Description

Tracing events with hardware components is one powerful tool to monitor, debug, and improve existing designs. Through this approach, detailed insights can be acquired, and peak performance can be achieved, while being a challenging task to be integrated with good performance. One of the major challenges of tracing is to collect as much information as possible with ideally no impact on the to-be-analyzed system. Herewith, it can be ensured that the gained insights are representative of an execution without any tracing enabled. In this work, a hardware tracing component should be leveraged to reduce the intrusiveness of existing software tracing mechanisms in the Linux kernel. 

This should be integrated and tested on a hardware platform based on a Xilinx Zynq board. This features a heterogeneous ARM multicore setup directly integrated into the ASIC, combined with programmable logic in the FPGA part of the chip. In the FPGA a hardware accelerator is already implemented that should be traced with the new component.

Prerequisites

To successfully complete this work, you should have:

  • experience with microcontroller programming,
  • basic knowledge about Git,
  • first experience with the Linux environment.

The student is expected to be highly motivated and independent.

Supervisor:

Lars Nolte

Development of a web application to control a hardware demonstration platform

Description

In this thesis, you lead the design and development of a web application to control a hardware demonstration platform and visualize the load of the available hardware resources, such as CPUs and hardware units. The used hardware platform is a Xilinx Zynq board. This features a heterogeneous ARM multicore setup directly integrated into the ASIC, combined with programmable logic in the FPGA part of the chip. In the FPGA, a hardware assist is implemented that improves blocking mechanisms in Linux by assisting the kernel with managing waiting threads. For further insights, the FPGA is also equipped with a 10G ethernet connection to send live data to a different PC for analysis and status information.

Responsibilities:

  • Understand the hardware demonstration platform's functionality and requirements for visualization and control.
  • Utilize your expertise in web development to design and create an interactive web application that visually represents hardware resource utilization (e.g., CPUs, hardware units) through graphs, charts, or other intuitive visualizations.
  • Develop a user-friendly control interface within the web application allowing users to start, manage, and monitor software applications running on the demonstration platform.
  • Conduct comprehensive testing, debugging, and optimization of the web application to ensure seamless functionality and performance.
  • Engage in regular meetings, providing updates on the project's progress, and actively participate in software design and implementation discussions.

 

Prerequisites

  • Experience with data visualization libraries or similar tools to create dynamic and informative visual representations.
  • First experience in web development projects, coursework, or internships showcasing relevant skills and expertise.
  • Understanding of hardware resource monitoring and visualization concepts and the ability to translate these into effective user interfaces.
  • Strong problem-solving skills, attention to detail, and the ability to work both independently and collaboratively in a team environment.
  • Knowledge of system administration or hardware-related concepts to facilitate seamless integration between the web application and the demonstration platform.

Contact

Email: lars.nolte@tum.de

Supervisor:

Lars Nolte

Non intrusive hardware tracing over ethernet

Description

Tracing of events in hardware components is one powerful tool to monitor, debug and improve existing designs. Through this approach detailed insights can be acquired and peak performance can be achieved, while being a challenging task to be integrated with good performance. One of the major challenges of tracing is to collect as much information as possible with ideally no impact on the to-be-analyzed system. Herewith, it can be ensured that the gained insights are representative of an execution without any tracing enabled. In this work, a hardware tracing component should be designed that takes an arbitrary data input and sends it via an ethernet connection to a different PC that performs the postprocessing of the data. The tracing component has to be designed in a way that for sending the data over ethernet no CPU involvement is required to minimize the impact on the traced system. This tracing component should be integrated into the hardware platform based on a Xilinx Zynq board. This features a heterogeneous ARM multicore setup directly integrated into the ASIC, combined with programmable logic in the FPGA part of the chip. In the FPGA a hardware accelerator is already implemented that should be traced with the new component.

Prerequisites

To successfully complete this work, you should have:

  • good HDL programming skills,
  • experience with microcontroller programming,
  • basic knowledge about Git,
  • first experience with the Linux environment.

The student is expected to be highly motivated and independent.

Contact

Email: lars.nolte@tum.de

Supervisor:

Lars Nolte

Comparing DPDK with traditional Linux based networking

Description

With the ever-increasing network speeds of physical links, the processing of packets on network nodes is becoming more and more of a bottleneck. Packet processing on a standard Linux-based network node traditionally involves the operating system (OS). Since an OS is usually optimized for a range of tasks rather than a specific task, using conventional Linux kernel functionalities for packet processing can degrade performance. For this reason, approaches to bypass the kernel have been proposed to perform network processing in user space.

One approach of bypassing the kernel that has attracted growing interest in recent years is Data Plane Development Kit (DPDK). By processing packets entirely in user space, DPDK avoids time-consuming context switches between user space and kernel space. This comes at the cost of one CPU core actively polling for new packets, instead of the network interface card (NIC) triggering interrupts for incoming packets. In addition, DPDK itself mainly provides the poll mode drivers for selected NICs, but the processing of the packets is the duty of the application using DPDK. Thus, while DPDK is suitable for certain application scenarios, there are also numerous use cases that are better suited to be implemented using the Linux networking stack. For example, to establish a Transmission Control Protocol (TCP) connection, an additional user space TCP/IP stack must be implemented or taken from open-source projects. These are generally not as feature-rich as the conventional Linux networking stack and do not necessarily improve performance.

This work aims to find a method to compare applications using DPDK with applications using the Linux network stack. Envisioned is a client-server application that uses iperf3 to generate data traffic.

Prerequisites

To successfully complete this work, you should have:

  • very good programming skills in Python and C/C++,
  • basic knowledge about Git,
  • first experience with the Linux environment.

The student is expected to be highly motivated and independent.

Contact

Email: lars.nolte@tum.de

Supervisor:

Lars Nolte

Completed Theses

2024

Bachelor's Theses

  • 24.01.2024
    Interprocess Communication: Signal events in user space with ueventfd and upipe
    Supervisor: Lars Nolte

2023

Bachelor's Theses

  • 30.10.2023
    Non-invasive integrated event tracing of FPGA via Ethernet
    Supervisor: Lars Nolte
  • 08.09.2023
    Non intrusive hardware tracing over ethernet
    Supervisor: Lars Nolte
  • 20.06.2023
    Optimization of Hardware Assisted Futex Implementation on Zynq Ultrascale+
    Supervisor: Lars Nolte
  • 20.03.2023 Maximilian Grözinger
    Digital Design and Validation of Hardware Assisted Futex - Implementation on Zynq Ultrascale+
    Supervisor: Lars Nolte

Master's Theses

  • 22.05.2023
    Hardware-assisting the User-Epoll mechanism in Linux
    Supervisor: Lars Nolte
  • 30.03.2023
    Optimizing high-speed network packet processing in Linux
    Supervisor: Lars Nolte

Research Internships (Forschungspraxis)

  • 20.12.2023
    Setting up L4Re on a Raspberry Pi
    Supervisor: Lars Nolte
  • 15.01.2023
    Implementation of a Finite State Machine for Hardware Managed Futexes on Zynq Ultrascale+
    Supervisor: Lars Nolte

2022

Bachelor's Theses

  • 09.03.2022
    Reduction of the Simulation Time of the Gem5 Simulator
    Supervisor: Lars Nolte

Master's Theses

  • 13.12.2022
    Digital Design and Validation of a Futex Hardware Accelerator – Emulation on Zynq Ultrascale+
    Supervisor: Lars Nolte

Research Internships (Forschungspraxis)

  • 30.09.2022
    Cache Coherent Hardware Accelerator Integration into an ARM Multicore Platform with a FPGA extension
    Supervisor: Lars Nolte
  • 12.06.2022
    Performance Improvement Evaluation of Hardware Accelerated Linux Thread Wake-ups
    Supervisor: Lars Nolte

Seminars

  • 20.07.2022
    [MSEI] A survey on asynchronous event notification mechanisms in Linux systems.
    Supervisor: Lars Nolte
  • 28.01.2022
    Survey on Linux Scheduler and Options to tweak an Application’s Performance
    Supervisor: Lars Nolte

Student Assistant Jobs

  • 31.07.2022
    Hardware Accelerator Integration into an ARM Multicore Platform with a FPGA extension
    Supervisor: Lars Nolte

2021

Bachelor's Theses

  • 01.12.2021
    Integration of Performance Counter into a simulation model of a hardware accelerator in Gem5.
    Supervisor: Lars Nolte
  • 13.09.2021
    Setup of an ARM Multicore Platform with a FPGA extension using a Xilinx Zynq Board and a Linux OS.
    Supervisor: Lars Nolte
  • 06.07.2021
    Low-intrusive Software Tracing and Profiling using a Gem5 Simulator
    Supervisor: Lars Nolte
  • 06.07.2021
    Low-intrusive Software Tracing and Profiling using a Gem5 Simulator
    Supervisor: Lars Nolte

Master's Theses

  • 13.12.2021
    Development of a Generic Framework for Linux Task Offloading to Hardware on a Multicore Architecture.
    Supervisor: Lars Nolte
  • 13.12.2021
    Development of a Generic Framework for Linux Task Offloading to Hardware on a Multicore Architecture.
    Supervisor: Lars Nolte

Research Internships (Forschungspraxis)

  • 12.05.2021
    Continuous Integration set up for a Gem5 Simulator project
    Supervisor: Lars Nolte

Seminars

  • 02.02.2021
    Application Profiling Tools in Linux
    Supervisor: Lars Nolte
  • 02.02.2021 Jonas Kirf
    A Survey on Inter-Process Communication
    Supervisor: Lars Nolte

Publications

2024

  • Lars Nolte, Tim Twardzik, Camille Jalier, Jiyuan Shi, Thomas Wild, Andreas Herkersdorf: POSTER: Hardware Assist for Linux IPC on an FPGA Platform. 21st ACM International Conference on Computing Frontiers, 2024 more… BibTeX Full text ( DOI )

2023

  • Lars Nolte, Tim Twardzik, Camille Jalier, Zhigang Huang, Jiyuan Shi, Clara Kowalsky, Thomas Wild, Andreas Herkersdorf: HAWEN: Hardware Accelerator for Thread Wake-Ups in Linux Event Notification. 2023 60th ACM/IEEE Design Automation Conference (DAC), 2023 more… BibTeX
  • Lars Nolte, Tim Twardzik, Camille Jalier, Zhigang Huang, Jiyuan Shi, Thomas Wild, Andreas Herkersdorf: HW-FUTEX: Hardware-Assisted Futex Syscall. IEEE Transactions on Very Large Scale Integration Systems, 2023 more… BibTeX Full text ( DOI )

2022

  • Lars Nolte, Tim Twardzik, Camille Jalier, Zhigang Huang, Jiyuan Shi, Thomas Wild, Andreas Herkersdorf: GLS Tracing: Gem5-based Low-intrusive Software Tracing. 2022 IEEE Nordic Circuits and Systems Conference (NorCAS), 2022 more… BibTeX

2021

  • Sven Rheindt, Akshay Srivatsa, Oliver Lenke, Lars Nolte, Thomas Wild, Andreas Herkersdorf: Tackling the MPSoC Data Locality Challenge – Part 2 / Chapter 5. In: Multi-Processor System-on-Chip 1. Wiley Online Library, 2021, 87-114 more… BibTeX

2020

  • Sven Rheindt, Andreas Fried, Oliver Lenke, Lars Nolte, Temur Sabirov, Tim Twardzik, Thomas Wild, Andreas Herkersdorf: X-CEL: A Method to Estimate Near-Memory Acceleration Potential in Tile-based MPSoCs. ARCS 2020 - 33rd International Conference on Architecture of Computing Systems, 2020 more… BibTeX
  • Sven Rheindt, Sebastian Maier, Nora Pohle, Lars Nolte, Oliver Lenke, Florian Schmaus, Thomas Wild, Wolfgang Schröder-Preikschat, Andreas Herkersdorf: DySHARQ: Dynamic Software-Defined Hardware-Managed Queues for Tile-Based Architectures. International Journal of Parallel Programming, 2020 more… BibTeX Full text ( DOI )

2019

  • Sven Rheindt, Andreas Fried, Oliver Lenke, Lars Nolte, Thomas Wild, Andreas Herkersdorf: NEMESYS: Near-Memory Graph Copy Enhanced System-Software. MEMSYS 19: The International Symposium on Memory Systems, 2019 more… BibTeX