Yuanji Ye, M.Sc.

Hardware prefetching is a technique used in modern processors to reduce memory access latency by predicting future data accesses and fetching data into the cache before it is explicitly requested by the processor. By exploiting regular access patterns, such as strided memory accesses, prefetchers can improve cache hit rate and overall system performance. 

This research internship focuses on the implementation of hardware prefetchers in modern processor cache systems. The intern will study the design and interfaces of HPDcache, which is already integrated into the CVA6 SoC. Based on this understanding, the intern will design and implement an IP-stride prefetcher and connect it to the HPDcache. The work also includes evaluating the implemented prefetcher using existing benchmarks on the FPGA board.

Through this internship, the student will gain hands-on experience in computer architecture, cache subsystem design, hardware integration, and experimental evaluation of prefetching techniques.

Prerequisites