CeCaS

Mannheim CeCaS is a supra-regional research project funded by the BMBF to develop a "Central Car Server" for future automated, connected and electrified vehicles. The project network consists of numerous industrial partners, accompanied by several academic research groups.

Overarching Objective: Automotive Supercomputing Platform - powerful Central Car Server concept based on new automotive qualified high performance processors, in FinFET supported by application specific accelerators and adaptive automotive SW stack for highly automated connected vehicles.

At the Technical University of Munich, three chairs (TUM-AIR, TUM-LIS, TUM-SEC) are involved in the CeCaS project network, contributing in the areas of model-based development, requirements management, software architecture, memory technology, and security.

 

Contribution of LIS

TUM-LIS is developing approaches for intelligent pre-fetching and write-back of data by the memory controller to increase the performance of the automotive processor. In addition, a prediction model for future addresses and data accesses is being investigated using machine learning methods such as reinforcement learning.

The current approach provides a wrapper layer around the DDR controller that realizes this functionality. It reduces the access latencies to external volatile and non-volatile main memories via adaptive prefetching of data and instructions in fast on-chip SRAM memories and by intelligent write-back of modified data located in the SRAM memory to the external main memory.

In the work on the wrapper layer we cooperate with TUM-SEC who investigate suitable lightweight techniques for transparent on-the-fly en-/de-cryption of data stored on external memory to prevent unauthorized access as well as error correction codes.

Workflow

In the CeCaS project we take a two-sided approach. On the one hand, we examine various implementation concepts and approaches with a SystemC based simulation model together with our partners. On the other hand, we are also working on an FPGA implementation, which offers a deeper level of abstraction for even more precise analyses. In both areas there are often topics for student work.

 

 

Involved Researchers

Open Student Work

Current Student Work

Evaluations-Framework für eine SystemC MPSoC Prototyp Architektur

Description

Gegenstand dieser Bachelorarbeit ist die Entwicklung eines Compile-Flows, mit dem verschiedene Benchmarks, z.B: von EEMBC, kompiliert und auf einer SystemC basierten Prototyp Architektur abgespielt werden können. Dabei sollen verschiedene Benchmarks, ggf. mit unterschiedlichen Parametern so in das System eingebunden werden, dass jedes Teammitglied diese auf einfache Weise kompilieren und abspielen kann.

Das SystemC Modell verwendet ein taktgenaues Modell eines Prozessors der Synopsys ARC Familie, um Speicherzugriffe auszuführen und so die Speicherhierarchie unter realistischen Bedingungen zu testen und zu evaluieren.

Je nach zeitlichem Fortgang der Arbeit kann man die Ergebnisse der Benchmarks dann  auswerten

Prerequisites

  • Gutes Fachwissen über MPSoC Systeme
  • Kenntnisse über Python-Programmierung
  • Hohe Motivation
  • Selbstverantwortliche Arbeitsweise

Contact

Oliver Lenke

o.lenke@tum.de

Supervisor:

Oliver Lenke

Analyse von Laufzeit-Statistiken eines SystemC MPSoC-Simulationsmodells mit Python

Description

Gegenstand dieser Bachelorarbeit ist die Entwicklung eines Python-Tools, welches die Ergebnisse (z.B. Log Files, Traces) eines SystemC Simulationsmodells auswertet und analysiert. Alle relevanten Events, zum Beispiel Speicherzugriffe, Cache Misses usw. werden dabei mit Zeitpunkt aufgezeichnet und bilden die Datenbasis für eine anschließende Performance-Evaluation.

Von besonderen Interesse sind dabei alle Performance-Statistiken, welche sich durch die Hardware-Prefetching Einheit ergeben, um deren Effektivität gezielt evaluieren zu können.

Aus diesen Traces sollen verschiedene Statistiken erstellt werden, dazu muss ein Python Programm geschrieben werden, welches die Traces auswertet und ggf. Plots erstellt.

Mögliche Statistiken sind beispielsweise

  • Auf welche Page wurde wie oft zugegriffen?
  • Wie viele Zugriffe hintereinander fallen im Schnitt in die selbe Page
  • Wie ist die zeitliche Verteilung der unterschiedlichen Pages?
  • Zeitlicher Abstand zwischen Zugriffen auf dieselbe Page?
  • Wie viele Pages wurden geladen, aber nicht genutzt?
  • Wie viele Speicherzugriffe fallen in vorgeladene Pages?

Diese Daten sollen bei der Analyse von Speicherzugriffsmustern von verschiedenen Anwendungen helfen, um so einen effizienten Mechanismus zum Vorladen ausgewählter Speicherinhalte zu entwickeln.

Prerequisites

  • Gutes Fachwissen über MPSoC Systeme
  • Kenntnisse über Python-Programmierung
  • Hohe Motivation
  • Selbstverantwortliche Arbeitsweise

Contact

Oliver Lenke

o.lenke@tum.de

Supervisor:

Oliver Lenke

Design and Implementation of a Stride Prefetching Mechanism in VHDL

Description

Since DRAM typically come with much higher access latencies than SRAM, many approaches to reduce DRAM latencies have already been explored, such as Caching, Access predictors, Row-buffers etc.

In the CeCaS research project, we plan to employ an additional mechanism, in detail a preloading mechanism of a certain fraction of the DRAM content to a small on-chip SRAM buffer. Thus, it is required to predict potentially next-accessed Cachelines, preload them to the SRAM and answer subsequent memory requests of this data from the SRAM instead forwarding them to the DRAM itself.

This functionality should be implemented as a cycle accurate VHDL model. A baseline system will bw provided, the goal is to implement this functionality in its simplest form as a baseline. Depending on the progress, this can be extended or refined in subsequent steps.

A close supervision, especially during the inital phase, will be guaranteed. Nevertheless, some experience with VHDL++ programming is required.

 

Prerequisites

  •    Experience with VHDL Coding
  •    Basic knowledge on MPSoC, cache hierarchies etc.
  •    B.Sc. in Electrical Engineering or similar

 

Supervisor:

Oliver Lenke

Python Tool zur Analyse von Speicherzugriffen

Description

Gegenstand dieser Bachelorarbeit ist die Entwicklung eines Python-Tools, welches verschiedene Statistiken über die Speicherzugriffe einer MPSoC-Architektur erstellt. Dazu werden simulations-basierte Traces verwendet, in denen alle Speicherzugriffe aufgezeichnet werden. In diesen Traces sind alle Zugriffe dokumientiert: Zeitpunkt? Cache Hit/Miss? Welcher Core?

Aus diesen Traces sollen verschiedene Statistiken erstellt werden, dazu muss ein Python Programm geschrieben werden, welches die Traces auswertet und Plottet.

Mögliche Statistiken sind beispielsweise

  • Auf welche Page wurde wie oft zugegriffen?
  • Wie viele Zugriffe hintereinander fallen im Schnitt in die selbe Page
  • Wie ist die zeitliche Verteilung der unterschiedlichen Pages?
  • Zeitlicher Abstand zwischen Zugriffen auf dieselbe Page?

Diese Daten sollen bei der Analyse von Speicherzugriffsmustern von verschiedenen Anwendungen helfen, um so einen effizienten Mechanismus zum Vorladen ausgewählter Speicherinhalte zu entwickeln.

Prerequisites

  • Gutes Fachwissen über MPSoC Systeme
  • Kenntnisse über Python-Programmierung
  • Hohe Motivation
  • Selbstverantwortliche Arbeitsweise

Contact

Oliver Lenke

o.lenke@tum.de

Supervisor:

Oliver Lenke

Development of a C Testsuite for a Memory Preloading Mechanism of an MPSoC

Keywords:
VHDL, C Programming, Distributed Memory, Data Migration, Task Migration, Hardware Accelerator

Description

Memory prefetching is a common technique used to hide memory access latencies and improve the performance of MPSoC architectures. In contrast to caches, data is read from the DRAM and stored in a fast on-chip buffer ahead of the actual CPU load request.

Such a memory prefetching mechanism is part of the TUM contribution to the CeCaS project and is currently under development. Besides a simulation environment, an FPGA-based prototype implementation was directly integrated into a State-of-the-Art MPSoC design.

The goal of this thesis is to develop a baremetal test environment for this preloading module to evaluate all possible corner cases. The testsuite  will be developed in a hardware-related C programming style and can be executed directly on the FPGA prototype platform.

Toward this goal, you will complete the following tasks:
1. Understanding the existing Memory Access and Preloading mechanism
2. Explore and understand possible corner-case scenarios
3. Develop a baremetal C program that triggers all corner cases
4. Analyse and discuss the results

Prerequisites

  • Good Knowledge about MPSoCs
  • Good C programming skills
  • High motivation
  • Self-responsible workstyle

Contact

Oliver Lenke

o.lenke@tum.de

Supervisor:

Oliver Lenke

Fine granular Page Preloading Mechanism on an FPGA Prototype

Keywords:
VHDL, C Programming, Distributed Memory, Data Migration, Task Migration, Hardware Accelerator

Description

Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density make DRAM omnipresend in most computer architectures. However, DRAM accesses are rather slow and require a dedicated DRAM controller
that coordinates the read and write accesses to the DRAM as well as the refresh cycles. In order to reduce the DRAM access latency, memory prefetching is a common technique to access data prior to their actual usage. However, this requires sophisticated prediction algorithms in order to prefetch the right data at the right time.


The Goal of this thesis is to refine an existing DRAM preloading mechanism on an  FPGA based prototype platform. Instead of preloading a whole memory page in a single atomic operation, the refinement should lead to a fine-granular page preloading, i.e. loading multiple small fractions of a page step by step while allowing regular memory accesses to be prioritized intermediately.


Towards this goal, you'll complete the following tasks:
1. Understanding the existing Memory Access and Preloading mechanism
2. VHDL implementation of the refined preloading functionalities
3. Write and execute small baremetal test programs
4. Analyse and discuss the performance results

Prerequisites

  • Good Knowledge about MPSoCs
  • Good VHDL skills
  • Good C programming skills
  • High motivation
  • Self-responsible workstyle

Contact

Oliver Lenke

o.lenke@tum.de

Supervisor:

Oliver Lenke

Completed Student Work

Supervisor:

Oliver Lenke

Contact

Oliver Lenke

o.lenke@tum.de

Supervisor:

Oliver Lenke

Supervisor:

Oliver Lenke

Student

Ali Emre Heybeli