Klajd Zyla, M.Sc.

Research Associate 

Technical University of Munich
TUM School of Computation, Information and Technology
Chair of Integrated Systems
Arcisstr. 21
80333 München
Germany

Tel.: +49.89.289.28560
Fax: +49.89.289.28323
Building: N1 (Theresienstr. 90)
Room: N2118
Email: klajd.zyla@tum.de

Curriculum Vitae

  • Since January 2022: Doctoral Candidate at LIS
  • 2019-2021: M.Sc. Electrical and Computer Engineering, TU Munich
    Area of specialization: Embedded and Computer Systems
    Master Thesis: Development of a Cooperative Multi-Agent RL Approach for Autonomous DVFS on MPSoCs
  • 2016-2019: B.Sc. Electrical and Computer Engineering, TU Munich
    Bachelor Thesis: Design of a Hardware-Based Debugger for a Self-Aware SoC Paradigm
  • Working student at LIS, INOVA Semiconductors GmbH and Dräxlmaier Group
  • Tutor for Electricity and Magnetism, Electromagnetic Field Theory

Research

My research focus lies in the development of architectures and methods for flexible and fast processing of data packets in high-performance SmartNICs. Important aspects in this context are the exploration of on-chip interconnects, the scheduling of packets with different priorities and the acceleration of transport protocols, such as RDMA (remote direct memory access).

Teaching

SystemC Laboratory (since SS 2022)

Student Projects

Available Projects

Ongoing Projects

Analysis and Comparison of FPGA-Optimized Network-On-Chips

Description

Network-on-chip (NoC) is a communication architecture used in multi-core and many-core systems to interconnect processing elements (PEs), such as CPUs, GPUs, accelerators, and memory controllers, using packet-switched networks similar to those found in computer networks. It replaces traditional bus-based interconnects with a scalable and modular network infrastructure, offering higher performance, lower latency, and improved scalability. In a NoC, PEs are connected through a network of routers and links, forming a mesh, torus, or other topologies. Each router is responsible for forwarding packets between neighboring PEs using routing algorithms. NoC architectures can vary greatly in terms of topology, routing algorithms, flow control mechanisms, and other parameters, depending on the specific application requirements and design constraints.

Field-Programmable Gate Arrays (FPGAs) are integrated circuits that contain an array of configurable logic blocks interconnected through programmable routing resources. They provide a versatile and powerful platform for implementing digital circuits and systems, offering flexibility, reconfigurability, parallelism, and hardware acceleration capabilities. Hence, they are well-suited for a wide range of applications across various domains, including telecommunications, networking, automotive, aerospace, consumer electronics, and industrial automation.

FPGA-optimized NoCs are tailored to exploit the unique features and capabilities of FPGAs while addressing the challenges of communication and interconnection in FPGA-based systems. They play a crucial role in enabling efficient and scalable communication infrastructure for FPGA-based applications across a wide range of domains. The goal of this seminar work is to investigate and compare state-of-the-art NoCs optimized for FPGAs.

Relevant literature

[1] Huan, Yutian, and André DeHon. "FPGA optimized packet-switched NoC using split and merge primitives." 2012 International Conference on Field-Programmable Technology. IEEE, 2012.

[2] Kapre, Nachiket, and Jan Gray. "Hoplite: Building austere overlay nocs for fpgas." 2015 25th international conference on field programmable logic and applications (FPL). IEEE, 2015.

[3] Monemi, Alireza, et al. "ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform." Microprocessors and Microsystems 54 (2017): 60-74.

Contact

Klajd Zyla

Email: klajd.zyla@tum.de

Supervisor:

Klajd Zyla

Development of a Network-On-Chip for Packet-Processing Architectures

Description

The fast pace at which new online services emerge leads to a rapid surge in the volume of network traffic. A recent approach that the research community has proposed to tackle this issue is in-network computing, which means that network devices perform more computations than before. As a result, processing demands become more varied, creating the need for flexible packet-processing architectures.

This project aims to develop a 2D-mesh network-on-chip (NoC) for a packet-processing architecture. An existing crossbar architecture can be used as a starting point for implementing the routers. The NoC should support XY routing and use the AXI4-Stream protocol to exchange data between modules. Exploring more complex algorithms, such as load-based minimal routing, is also possible. Moreover, the routers can be extended to consider the priorities of incoming packets when making scheduling decisions. The NoC should be implemented in Verilog and integrated into the existing packet-processing architecture. The achievable throughput and per-packet latency should be evaluated via cycle-accurate register-transfer level simulations. Furthermore, it should be synthesized and implemented in Vivado. Optionally, it can be tested with real-world network traffic on an FPGA.

Supervisor:

Klajd Zyla

Finished Projects

Contact

Supervisor:

Klajd Zyla

Student

Rei Haskaj

Contact

Supervisor:

Klajd Zyla

Student

Antra Pramanik

Supervisor:

Klajd Zyla

Student

Amna Bouzaida

Supervisor:

Klajd Zyla

Student

Antra Pramanik

Contact

Supervisor:

Klajd Zyla

Student

Sujie Zhang

Contact

Supervisor:

Klajd Zyla

Student

Johannes Ecker

Supervisor:

Klajd Zyla

Student

Kejdi Guzi

Contact

Supervisor:

Klajd Zyla

Student

Quentin Georges André VERMOT d

Contact

Supervisor:

Klajd Zyla

Student

Mustafa Ergün

Contact

klajd.zyla@tum.de

Supervisor:

Klajd Zyla

Student

Kejdi Guzi

Publications

  • Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf: FlexRoute: A Fast, Flexible and Priority-Aware Packet-Processing Design. 32nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP 2024), 2024 more… BibTeX Full text ( DOI )
  • Klajd Zyla, Florian Maurer, Thomas Wild, Andreas Herkersdorf: CoLeCTs: Cooperative Learning Classifier Tables for Resource Management in MPSoCs. 36th GI/ITG International Conference on Architecture of Computing Systems, 2023 more… BibTeX Full text ( DOI )
  • Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf: FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance SmartNICs. 31st IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2023), 2023 more… BibTeX Full text ( DOI )