
Klajd Zyla, M.Sc.
Research Associate
Technical University of Munich
TUM School of Computation, Information and Technology
Chair of Integrated Systems
Arcisstr. 21
80333 München
Germany
Tel.: +49.89.289.28560
Fax: +49.89.289.28323
Building: N1 (Theresienstr. 90)
Room: N2118
Email: klajd.zyla@tum.de
Curriculum Vitae
- Since January 2022: Doctoral Candidate at LIS
- 2019-2021: M.Sc. Electrical and Computer Engineering, TU Munich
Area of specialization: Embedded and Computer Systems
Master Thesis: Development of a Cooperative Multi-Agent RL Approach for Autonomous DVFS on MPSoCs - 2016-2019: B.Sc. Electrical and Computer Engineering, TU Munich
Bachelor Thesis: Design of a Hardware-Based Debugger for a Self-Aware SoC Paradigm - Working student at LIS, INOVA Semiconductors GmbH and Dräxlmaier Group
- Tutor for Electricity and Magnetism, Electromagnetic Field Theory
Research
My research focus lies in the development of architectures and methods for flexible and fast processing of data packets in high-performance SmartNICs. Important aspects in this context are the exploration of on-chip interconnects, the scheduling of packets with different priorities and the acceleration of transport protocols, such as RDMA (remote direct memory access).
Analysis and Comparison of Interconnects for Packet-Processing Designs
Description
Switches and network interface cards receive traffic at hundreds of Gbit/s and process packets with stringent latency requirements. The bandwidth and forwarding latency of the interconnect highly affects the performance of the whole design. The goal of this seminar work is to investigate and compare state-of-the-art interconnects in terms of metrics such as throughput, latency, priority-awareness, scalability and chip area.
[1] Kurth, Andreas, et al. "An open-source platform for high-performance non-coherent on-chip communication." IEEE Transactions on Computers 71.8 (2021): 1794-1809.
[2] Lin, Jiaxin, et al. "PANIC: A high-performance programmable NIC for multi-tenant networks." Proceedings of the 14th USENIX Conference on Operating Systems Design and Implementation. 2020.
Contact
Email: klajd.zyla@tum.de
Supervisor:
Analysis and Comparison of Interconnects for Packet-Processing Designs
Description
Switches and network interface cards receive traffic at hundreds of Gbit/s and process packets with stringent latency requirements. The bandwidth and forwarding latency of the interconnect highly affects the performance of the whole design. The goal of this seminar work is to investigate and compare state-of-the-art interconnects in terms of metrics such as throughput, latency, priority-awareness, scalability and chip area.
[1] Kurth, Andreas, et al. "An open-source platform for high-performance non-coherent on-chip communication." IEEE Transactions on Computers 71.8 (2021): 1794-1809.
[2] Lin, Jiaxin, et al. "PANIC: A high-performance programmable NIC for multi-tenant networks." Proceedings of the 14th USENIX Conference on Operating Systems Design and Implementation. 2020.
Contact
Email: klajd.zyla@tum.de
Supervisor:
Implementation of a Packet-Processing Design on an FPGA
Description
FlexRoute is a packet-processing architecture where offloads are arranged sequentially in the order that they are intended to be used. Each offload contains two forwarding channels in order to enable recirculation of packets through the sequence of offloads even when packets are coming back to back. It also consists of flexible forwarding logic that bypasses the corresponding processing units if their functionality is not needed by an incoming packet in order to reduce latency. Furthermore, it contains a scheduler that steers traffic to the least loaded processing unit and priority-aware traffic arbiters that privilege high-priority packets when traffic from multiple sources needs to exit the offload.
We have shown the potential benefit of our proposed design via cycle-accurate register-transfer level (RTL) simulations in Xilinx Vivado. The goal of this project is to synthesize and implement the design on an FPGA by using Vivado. Moreover, the design should be tested by injecting network traffic via Ethernet and measuring the throughput and the per-packet latency.
Prerequisites
- Good knowledge of the basics of digital circuits, especially regarding timing analysis
- Experience with hardware description languages (HDL), such as VHDL or Verilog
- Preferably experience with electronic design automation (EDA) tools, such as Xilinx Vivado
Supervisor:
Analysis and Comparison of Interconnects for Packet-Processing Designs
Description
Switches and network interface cards receive traffic at hundreds of Gbit/s and process packets with stringent latency requirements. The bandwidth and forwarding latency of the interconnect highly affects the performance of the whole design. The goal of this seminar work is to investigate and compare state-of-the-art interconnects in terms of metrics such as throughput, latency, priority-awareness, scalability and chip area.
[1] Kurth, Andreas, et al. "An open-source platform for high-performance non-coherent on-chip communication." IEEE Transactions on Computers 71.8 (2021): 1794-1809.
[2] Lin, Jiaxin, et al. "PANIC: A high-performance programmable NIC for multi-tenant networks." Proceedings of the 14th USENIX Conference on Operating Systems Design and Implementation. 2020.
Contact
Email: klajd.zyla@tum.de
Supervisor:
Supervisor:
Student
Supervisor:
Student
Contact
klajd.zyla@tum.de
Supervisor:
- CoLeCTs: Cooperative Learning Classifier Tables for Resource Management in MPSoCs. 36th GI/ITG International Conference on Architecture of Computing Systems, 2023 more… BibTeX Full text ( DOI )
- FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance SmartNICs. 31st IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2023), 2023 more… BibTeX Full text ( DOI )