Tim Twardzik, M.Sc.

Wissenschaftlicher Mitarbeiter

Technische Universität München
School of Computation, Information and Technology
Lehrstuhl für Integrierte Systeme
Arcisstr. 21
80333 München

Tel.: +
Fax: +
Gebäude: N1 (Theresienstr. 90)
Raum: N2115
Email: tim.twardzik@tum.de

Offered Work

Are you interested in an intership or thesis eventhough no work is currently offered here? Feel free to contact me directly via email.

Ongoing Work

A Survey on Benchmarking Systems

Benchmark, Linux


As technology advances, the performance of CPUs plays a crucial role in various computational tasks ranging from everyday computing to specialized applications like gaming, artificial intelligence, and scientific simulations. Benchmarking CPU performance helps in understanding and comparing the capabilities of different processors across various workloads. This seminar topic aims to conduct a comprehensive survey on benchmark suites commonly used for evaluating CPU performance.

For this, various state-of-the-art benchmark suites should be analyzed and compared against each other based on pre-defined criteria.

The goal of this survey is to generate an overview and comparative analysis of the different benchmark suites that are available and focus on their unique approaches.


Tim Twardzik

Developement and Evaluation of a Hardware Thread Scheduler on a FPGA


In modern computing systems, efficient resource management is crucial for maximizing performance and ensuring fair resource allocation among tasks. One critical aspect of resource management is thread scheduling, which involves determining the order and timing of execution for concurrent tasks or threads. In this project, we propose to implement a hardware-based thread scheduler on a Field-Programmable Gate Array (FPGA).


  • Design and implement a hardware-based thread scheduler
  • Integrate the scheduler into existing FPGA prototype
  • Test and Evaluate the design

Tasks include:

  1. Understanding the underlying software mechanisms for thread scheduling
  2. Designing the hardware scheduler
  3. Implementing the design in HDL
  4. Testing the design

Implementing a hardware thread scheduler on an FPGA offers significant advantages in terms of performance, efficiency, and inter-process communication. This project aims to explore the design, implementation, and evaluation of such a scheduler.


Tim Twardzik


  • Lars Nolte, Tim Twardzik, Camille Jalier, Zhigang Huang, Jiyuan Shi, Thomas Wild, Andreas Herkersdorf: HW-FUTEX: Hardware-Assisted Futex Syscall. IEEE Transactions on Very Large Scale Integration Systems, 2023 more… BibTeX Full text ( DOI )
  • Lars Nolte, Tim Twardzik, Camille Jalier, Zhigang Huang, Jiyuan Shi, Clara Kowalsky, Thomas Wild, Andreas Herkersdorf: HAWEN: Hardware Accelerator for Thread Wake-Ups in Linux Event Notification. 2023 60th ACM/IEEE Design Automation Conference (DAC), 2023 more… BibTeX
  • Lars Nolte, Tim Twardzik, Camille Jalier, Zhigang Huang, Jiyuan Shi, Thomas Wild, Andreas Herkersdorf: GLS Tracing: Gem5-based Low-intrusive Software Tracing. 2022 IEEE Nordic Circuits and Systems Conference (NorCAS), 2022 more… BibTeX
  • Sven Rheindt, Andreas Fried, Oliver Lenke, Lars Nolte, Temur Sabirov, Tim Twardzik, Thomas Wild, Andreas Herkersdorf: X-CEL: A Method to Estimate Near-Memory Acceleration Potential in Tile-based MPSoCs. ARCS 2020 - 33rd International Conference on Architecture of Computing Systems, 2020 more… BibTeX