Shichen Huang, M.Sc.
Research Associate
Technical University of Munich
TUM School of Computation, Information and Technology
Chair of Integrated Systems
Arcisstr. 21
80333 Munich
Germany
Phone: +49.89.289.23858
Fax: +49.89.289.28323
Building: N1 (Theresienstr. 90)
Room: N2116
Email: shichen.huang@tum.de
Research Interests
My research interests include computer and network architecture, with a focus on efficient communication and synchronization in networked systems.
If you are motivated and nothing is displayed here, please feel free to send me an email (after taking a look at my research interests).
Ongoing Student Work
Efficient Packet Arrival-Location Resolution for Distributed Packet Processing
Description
Background
Modern networked systems increasingly rely on virtualization, indirection, and pooled accelerator resources to improve scalability and resource utilization. In emerging DPU- or SmartNICbased pooling architectures, processing a packet may require access to, or updates of, flow-, connection-, or protocol-related context maintained by other DPUs. For example, a packet may arrive at one DPU or SmartNIC, while the relevant state context for the corresponding flow or connection may reside on another DPU.
This breaks the traditional assumption that packet arrival and packet processing naturally happen at the same location. In a distributed processing environment, the arrival location of each packet is not automatically known to all relevant processing entities. Therefore, the system needs an efficient mechanism to inform the responsible DPUs where packets have arrived.
In the context of distributed packet processing, this issue becomes especially important for single-flow processing, where packets belonging to the same flow may require ordered processing, shared state access, or state synchronization across multiple DPUs.
Objective
The objective of this FP is to design and evaluate an efficient packet arrival-location resolution mechanism for distributed DPU/SmartNIC-based packet processing.
A straightforward solution is to broadcast or multicast the arrival information of every packet to all relevant DPUs. However, this approach can consume a large amount of interconnect bandwidth, especially under high packet rates or larger DPU pools. Therefore, this project aims to develop a more scalable mechanism with lower communication overhead.
The student is expected to analyze the limitations of baseline approaches, identify the key design trade-offs, and propose an improved arrival-location resolution scheme. The proposed scheme should be evaluated with respect to notification latency, bandwidth consumption, metadata or storage overhead, and scalability.
Evaluation
The proposed solution will be evaluated in comparison with the baseline models.
If a suitable gem5-based simulation model is available in time, the mechanisms may be implemented and evaluated in C++ within the gem5 simulation environment. Otherwise, the student will build an event-driven timing-level simulation model in Python.
The main evaluation metrics include:
- Arrival-location notification latency: the time between the physical arrival of a packet at one DPU and the moment when the relevant target DPU or target DPU group becomes aware of the packet’s arrival location.
- Inter-DPU bandwidth consumption: the amount of communication traffic introduced by the discovery or advertising mechanism.
- Metadata or storage overhead: the number of bits required per packet, flow, table entry, or local arrival-location table, depending on the mechanism.
- Scalability: the behavior of the mechanism as the number of DPUs in the target DPU group increases, for example from 2 to 8 DPUs.
Although the student may seek inspiration from general distributed systems, where problem occur as: when work arrives at one node but may need the context on another node, the system must efficiently advertise or discover the arrival location while avoiding excessive communication overhead, the arrival-location resolution mechanism should be evaluated with a simplified pipelinebased packet-processing model, rather than in a stand-alone general distributed processing scenario. In addition, the evaluation should discuss how arrival-location resolution affects packet-processing progress.
Baseline Models
The project should compare the proposed mechanism against the following baseline or reference models.
- Broadcast or Multicast upon Every Packet Arrival: In this baseline, whenever a packet arrives at a DPU, the arrival information is broadcast or multicast to all relevant DPUs. This approach is simple and ensures that all DPUs can learn the packet arrival location, but it may introduce significant bandwidth overhead.
- Timely Advertising: In this model, several advertising strategies are combined with a local arrival-location table. The table records where packets have arrived and allows responsible DPUs to advertise packet arrival in a timely manner. Further details of this model will be provided by the supervisor during the project. The student is expected to implement, compare, and discuss these models with respect to their notification latency, bandwidth consumption, metadata/storage overhead, and scalability.
Prerequisites
The student should have the following background:
- Basic knowledge of computer networks, including the OSI 7-layer model
- Basic knowledge of computer architecture, especially SoC design and on-chip/off-chip interconnects
- Basic knowledge of RDMA and RoCE
- Good programming skills in Python
- Good programming skills in C++
- Interest in distributed systems, network acceleration, and DPU/SmartNIC-based architectures
Knowledge of DPUs, SmartNICs, or gem5 is helpful but not strictly required.
Contact
shichen.huang@tum.de
Supervisor:
Synchronization in stateful network processing
Description
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Contact
shichen.huang@tum.de
Supervisor:
Completed Student Work
Contact
Shichen Huang
shichen.huang@tum.de
Supervisor:
Contact
Dr. Stephan Herrmann
NXP Semiconductors Germany, Munich
Email: stephan.herrmann@nxp.com
Supervisor:
Contact
shichen.huang@tum.de
Supervisor:
Contact
Dr. Stephan Herrmann
NXP Semiconductors Germany, Munich
Email: stephan.herrmann@nxp.com
Supervisor:
Contact
shichen.huang@tum.de