Bachelor Theses

With the advent of research on the next generation of
mobile communications 6G, we are engaged in exploring
architecture extensions for Smart Network Interface Cards
(SmartNICs). To enable adaptive, energy-efficient and
low-latency network interfaces, we are prototyping a
custom packet processing pipeline on FPGA-based NICs,
partially based on the open-nic project
(https://github.com/Xilinx/open-nic).

Incoming packet flows should be differentiated and differently
processed, which is typically solved with match-action tables (MATs).
MATs match on a certain packet condition (e.g. packet header 5-tuple) and execute an according action (e.g. dropping, forwarding or modifying the packet). A recent Xilinx IP core implements MATs that can be programmed with P4, a programmable packet processing language gaining momentum in networking. The goal of this work is to investigate the implementation of MATs in hardware, integrate them into our current HDL design based on open-nic and test and evaluate the results.

•     Programming skills in VHDL/Verilog and C (and Python)
•     Practical experience with FPGA Design and Implementation
•     Good Knowledge of computer networks, OSI layer model and protocols
•     Preferably basic knowledge of P4 packet processing language

At LIS, we want to use the Duckietown hardware and software ecosystem to experiment with our reinforcement learning-based learning classifier tables (LCT) as part of the control system of the Duckiebots: https://www.ce.cit.tum.de/lis/forschung/aktuelle-projekte/duckietown-lab/.

More information on Duckietown can be found at https://www.duckietown.org/.

In this student work, we want to extend the bot's current abilities (lane following).

The goal of this work is to enable the bots to follow each other with a constant distance.
At the end, there should be a seamless integration in the Lane Following Pipeline.

• Knowledge about Image Processing
• Python

At LIS, we want to use the Duckietown hardware and software ecosystem to experiment with our reinforcement learning-based learning classifier tables (LCT) as part of the control system of the Duckiebots: https://www.ce.cit.tum.de/lis/forschung/aktuelle-projekte/duckietown-lab/.

More information on Duckietown can be found at https://www.duckietown.org/.

In this student work, we want to extend the bot's current abilities (lane following).

The goal of this work is to enable the bots to avoid obstacles on the road (e.g. ducks, other bots, ...) and to stop at intersections (red lines) for a predefined time.
At the end, there should be a seamless integration in the Lane Following Pipeline.

• Knowledge about Image Processing
• Python

In modern computing systems, efficient resource management is crucial for maximizing performance and ensuring fair resource allocation among tasks. One critical aspect of resource management is thread scheduling, which involves determining the order and timing of execution for concurrent tasks or threads. In this project, we propose to implement a hardware-based thread scheduler on a Field-Programmable Gate Array (FPGA).

Objectives:

• Design and implement a hardware-based thread scheduler
• Integrate the scheduler into existing FPGA prototype
• Test and Evaluate the design

Tasks include:

1. Understanding the underlying software mechanisms for thread scheduling
2. Designing the hardware scheduler
3. Implementing the design in HDL
4. Testing the design

Implementing a hardware thread scheduler on an FPGA offers significant advantages in terms of performance, efficiency, and inter-process communication. This project aims to explore the design, implementation, and evaluation of such a scheduler.

With the advent of research on the next generation of
mobile communications 6G, we are engaged in exploring
architecture extensions for Smart Network Interface Cards
(SmartNICs). To enable adaptive, energy-efficient and
low-latency network interfaces, we are prototyping a
custom packet processing pipeline on FPGA-based NICs,
partially based on the open-nic project
(https://github.com/Xilinx/open-nic).

To improve the performance and energy efficiency of a
modern server, SmartNICs can be used to preprocess
incoming packets and gather characteristics on traffic and processing requirements. This information can be used to change the processing behavior of the server and react to the dynamic network and processing requirements. To do so, the server has to be notified of detected events using an interrupt.

The goal of this work is to implement hardware-based interrupt generation in an FPGA-based SmartNIC using HDL and PCIe IP cores, registering the interrupt with the Linux interrupt driver as well as writing a suitable ISR (interrupt service routine). This mechanism should be functionally verified in a hardware testbed and evaluated regarding the latency of the interrupt. Additionally, the work could be extended to include setting the core affinity of an interrupt and generating interrupts destined for specific CPU cores.

• Programming skills in VHDL/Verilog and C (and Python)
• Practical experience with FPGA Design and Implementation
• Good Knowledge of computer architecture and low-level software / drivers
• Comfortable with the Linux command line and bash

With the advent of research on the next generation of
mobile communications 6G, we are engaged in exploring
architecture extensions for Smart Network Interface Cards
(SmartNICs). To enable adaptive, energy-efficient and
low-latency network interfaces, we are prototyping a
custom packet processing pipeline on FPGA-based NICs,
partially based on the open-nic project
(https://github.com/Xilinx/open-nic).

To properly evaluate the performance of a
SmartNIC-assisted server, a webserver-based application
shall be setup in a Linux OS environment and tested with different request rates. Additionally, the performance of single- vs. multicore platforms for one and multiple webserver instances should be compared. CPU core isolation mechanisms can be used to setup such scenarios on the server.

The goal of this work is to setup a webserver (e.g. NGINX), potentially with a database backend (e.g. MongoDB) and develop a measurement and testing methodology for performance benchmarking of a SmartNIC-assisted server. This includes throughput and latency measurements, as well as analysis of the CPU and network utilization.

•     Programming skills C and Python
•     Good Knowledge of computer networks, OSI layer model and protocols
•     Comfortable with the Linux command line and bash
•     Preferably experience with Linux drivers and low-level software

With the advent of research on the next generation of
mobile communications 6G, we are engaged in exploring
architecture extensions for Smart Network Interface Cards
(SmartNICs). To enable adaptive, energy-efficient and
low-latency network interfaces, we are prototyping a
custom packet processing pipeline on FPGA-based NICs,
partially based on the open-nic project
(https://github.com/Xilinx/open-nic).

Load balancing is a challenging task in modern data
centers and servers, as the number of processing cores rises (96 cores in recent AMD Epyc platforms) and the packet processing workload should be distributed equally among them. To assist this process, incoming packet flows should be differentiated and assigned to different queues already in the NIC hardware. These queues must then be pinned to different processor cores to ensure the hardware load-balancing algorithm works correctly.

The goal of this work is to implement the queue assignment in the FPGA SmartNIC platform using HDL, configuring the NIC driver to use the correct queues, and pinning the processing of the queues onto different CPU cores. Further, functional verification as well as performance evaluation should be done on the system.

•     Programming skills in VHDL/Verilog and C (and Python)
•     Practical experience with FPGA Design and Implementation
•     Good Knowledge of computer networks, OSI layer model and protocols
•     Comfortable with the Linux command line and bash

The fast pace at which new online services emerge leads to a rapid surge in the volume of network traffic. A recent approach that the research community has proposed to tackle this issue is in-network computing, which means that network devices perform more computations than before. As a result, processing demands become more varied, creating the need for flexible packet-processing architectures.

This project aims to develop a 2D-mesh network-on-chip (NoC) for a packet-processing architecture. An existing crossbar architecture can be used as a starting point for implementing the routers. The NoC should support XY routing and use the AXI4-Stream protocol to exchange data between modules. Exploring more complex algorithms, such as load-based minimal routing, is also possible. Moreover, the routers can be extended to consider the priorities of incoming packets when making scheduling decisions. The NoC should be implemented in Verilog and integrated into the existing packet-processing architecture. The achievable throughput and per-packet latency should be evaluated via cycle-accurate register-transfer level simulations. Furthermore, it should be synthesized and implemented in Vivado. Optionally, it can be tested with real-world network traffic on an FPGA.