Tim Twardzik, M.Sc.

As technology advances, the performance of CPUs plays a crucial role in various computational tasks ranging from everyday computing to specialized applications like gaming, artificial intelligence, and scientific simulations. Benchmarking CPU performance helps in understanding and comparing the capabilities of different processors across various workloads. This seminar topic aims to conduct a comprehensive survey on benchmark suites commonly used for evaluating CPU performance.

For this, various state-of-the-art benchmark suites should be analyzed and compared against each other based on pre-defined criteria.

The goal of this survey is to generate an overview and comparative analysis of the different benchmark suites that are available and focus on their unique approaches.

In modern computing systems, efficient resource management is crucial for maximizing performance and ensuring fair resource allocation among tasks. One critical aspect of resource management is thread scheduling, which involves determining the order and timing of execution for concurrent tasks or threads. In this project, we propose to implement a hardware-based thread scheduler on a Field-Programmable Gate Array (FPGA).

Objectives:

• Design and implement a hardware-based thread scheduler
• Integrate the scheduler into existing FPGA prototype
• Test and Evaluate the design

Tasks include:

1. Understanding the underlying software mechanisms for thread scheduling
2. Designing the hardware scheduler
3. Implementing the design in HDL
4. Testing the design

Implementing a hardware thread scheduler on an FPGA offers significant advantages in terms of performance, efficiency, and inter-process communication. This project aims to explore the design, implementation, and evaluation of such a scheduler.