Bachelorarbeiten

In this thesis, you lead the setup of the L4Re (L4 Runtime Environment) on Raspberry Pi devices. This is an exciting opportunity to work on cutting-edge technology, combining the flexibility of L4 microkernel architecture with the capabilities of Raspberry Pi to build secure and modular operating systems for embedded systems.

You will delve into the fascinating world of microkernel architecture. Unlike traditional monolithic kernels, where most functionality resides within the kernel, microkernels follow a minimalist approach. The microkernel serves as a lightweight core, providing only essential services such as interprocess communication (IPC) and memory management. Additional operating system services and functionalities, including device drivers and file systems, are implemented as separate user-level processes or servers that run outside the microkernel.

Responsibilities:

• Set up and configure the development environment for L4Re on Raspberry Pi, including toolchain and cross-compilation environment.
• Obtain the L4Re source code by downloading from the official repository or using a specific release.
• Build the L4Re system for Raspberry Pi, ensuring successful compilation and linking of components.
• Deploy the compiled L4Re system onto Raspberry Pi boards, including bootloader setup and configuration.
• Test and verify the functionality and performance of the L4Re system on Raspberry Pi, conducting both functional and security evaluations.
• Develop custom components and applications on top of L4Re, integrating them into the system and extending its functionality.
• Document the setup process, configurations, and customizations, ensuring clear and concise documentation for future reference.

• Solid understanding of embedded systems development and experience with low-level programming.
• Proficiency in C/C++ programming languages and familiarity with cross-compilation environments.
• Strong knowledge of operating system concepts and microkernel architectures, preferably with experience working with L4-based systems.
• Experience with Raspberry Pi development and configuration, including bootloader setup and deployment.
• Familiarity with embedded Linux, device drivers, and system-level software development.
• Excellent problem-solving skills and the ability to troubleshoot complex issues.

Since DRAM typically come with much higher access latencies than SRAM, many approaches to reduce DRAM latencies have already been explored, such as Caching, Access predictors, Row-buffers etc.

In the CeCaS research project, we plan to employ an additional mechanism, in detail a preloading mechanism of a certain fraction of the DRAM content to a small on-chip SRAM buffer. Thus, it is required to predict potentially next-accessed Cachelines, preload them to the SRAM and answer subsequent memory requests of this data from the SRAM instead forwarding them to the DRAM itself.

This functionality should be implemented as a TLM/SystemC model using Synopsys Platform Architect. A baseline system will bw provided, the goal is to implement this functionality in its simplest form as a baseline. Depending on the progress, this can be extended or refined in subsequent steps.

A close supervision, especially during the inital phase, will be guaranteed. Nevertheless, some experience with TLM modelling (e.g. SystemC Lab of LIS) or C++ programming is required.

• Experience with TLM modelling (e.g. SystemC Lab of LIS)
• B.Sc. in Electrical Engineering or similar

At LIS, we want to use the Duckietown hardware and software ecosystem for experimenting with our reinforcement learning based learning classifier tables (LCTs) as part of the control system of the Duckiebots: https://www.ce.cit.tum.de/lis/forschung/aktuelle-projekte/duckietown-lab/

More information on Duckietown can be found on https://www.duckietown.org/.

Currently, we are developing the infrastructure for our LCT experiments.
While several students are improving on the autonomous driving abilities of the Duckiebots, this work's goal is to develop a system which provides insights into the bots' driving performance.
Therefore, we need objective measurements by a third party which allow us to compare the driving performance (average speed, deviation from optimal line, …) between bots which might run different SW.
To compare specific scenarios, these measurements shouldn't only be a time series, but be enhanced by the position of the respective bot at this point in time. Similar to the modern sports apps: https://www.outdooractive.com/de/route/wanderung/tegernsee-schliersee/auf-dem-prinzenweg-vom-schliersee-an-den-tegernsee/1374189/#dm=1.

Towards this goal it's required to develop a camera-based mechanism, which identifies bots in the field, extracts their concrete position and calculates certain metrics like direction, velocity, on / off lane, spinning, deviation from ideal line, ….
This data then should be logged to be analyzed + visualized later.

Depending on the type of work (BA/FP vs MA) this work might include to enhance these measurements with internal data of the bots to compare internal and external perception, and to develop tools for easy analysis.

• independent work style
• problem solving skills
• computer vision knowledge (openCV)
• programming skills (we are open which framework is used - Python, C++ (Qt), Matlab, ...
• Linux basics (permissions)

With the advent of research on the next generation of
mobile communications 6G, LIS is engaged in exploring
architectures and architecture extensions for networking
hardware. In order to research on energy-efficient and
low-latency network interfaces for next-generation
networks, we are setting up a hardware testbed with
FPGA-based Network Interface Accelerator Cards in the
form of Xilinx Alveo and NetFPGA SUME FPGA boards.
This requires the bring-up and evaluation of the  HDL
Design, the Linux kernel drivers and applications.

OpenNIC provides open-source code for an HDL design and kernel driver as basis for a custom hardware network interface on FPGAs. The goal of this work is to configure and setup the project on the available hardware resources at our chair. This includes analyzing the open-source designs, establishing a workflow to modify given designs with proper hardware and software design tools, documentation and integration and testing the correct functionality of both hardware and software. As an additional task, the setup could be evaluated concerning key performance indicators (KPIs) such as latency, bandwidth, memory footprint, etc. This can also involve the creation of custom tests in (both) hardware and software.

- Good experience with Linux, Command Line Tools and Bash scripting
- Programming skills in VHDL/Verilog and C (and Python)
- Preferably experience with FPGA Design and Implementation

XCS is a class of human-interpretable machine learning algorithm which combines the concepts of machine learning from reinforcement learning and the pattern recognition property of genetic algorithms. XCS operates my maintaining a population of classifiers. Experience replay is a popular strategy used in machine learning to speed the process of learning and improve performance.

In this work, you will

1. Understand the XCS algrorithm and its implementation in python.

2. Implement dynamic sized ER buffer for the XCS.

3. Experiment your work on various benchmarks used in the machine learning domain.

4. Compare your results against an XCS without ER and an XCS with fixed size ER.

To successfully complete this project, you should already have the following skills and experiences:

• Good python skills
• Basic knowledge of machine learning
• Self-motivated and structured work style

Reinforcement learning (RL) has been widely used for run-time management on multi-core processors. RL-based controllers can adapt to varying emerging workloads, system goals, constraints and environment changes by learning from their experiences.

Neural Networks are a set of ML methods which are inspired by the human brain, mimicking the way that biological neurons signal to one another.

In this work, you will

1. Understand the working of Neural Networks. Implement a neural network in C.

2. Understand the architecture of the Leon3 based SoC.

3. Use neural networks to learn and control the processor voltage and frequency in runtime to optimize performance and power.

4. Design, test and implement the work on Xilinx FPGA

To successfully complete this project, you should already have the following skills and experiences: 
• Good VHDL and C programming skills 
• Good understanding of MPSoCs
• Self-motivated and structured work style
• Knowledge of machine learning algorithms

In order to research on energy-efficient and
low-latency network nodes for next-generation
networks, we are setting up a hardware testbed
with FPGA-based Network Interface Accelerator
Cards in the form of Xilinx Alveo FPGA boards.
Previous research in the area of Network Interface
Cards (NICs) at our chair led to HDL Designs of
Packet Processing Pipelines on older generation
FPGAs, which shall serve as basis for further research on Xilinx Alveo FPGA boards.

Therefore, the goal of this work is to port these existing HDL Designs to the new FPGAs. This includes analyzing the existing designs, extracting the required logic and integrating it into the OpenNIC framework. Further, the functionality of the designs has to be verified by testing.

- Experience with Linux, Command Line Tools and Bash scripting
- Programming skills in VHDL/Verilog and C (and Python)
- Experience with FPGA Design and Implementation

Tracing of events in hardware components is one powerful tool to monitor, debug and improve existing designs. Through this approach detailed insights can be acquired and peak performance can be achieved, while being a challenging task to be integrated with good performance. One of the major challenges of tracing is to collect as much information as possible with ideally no impact on the to-be-analyzed system. Herewith, it can be ensured that the gained insights are representative of an execution without any tracing enabled. In this work, a hardware tracing component should be designed that takes an arbitrary data input and sends it via an ethernet connection to a different PC that performs the postprocessing of the data. The tracing component has to be designed in a way that for sending the data over ethernet no CPU involvement is required to minimize the impact on the traced system. This tracing component should be integrated into the hardware platform based on a Xilinx Zynq board. This features a heterogeneous ARM multicore setup directly integrated into the ASIC, combined with programmable logic in the FPGA part of the chip. In the FPGA a hardware accelerator is already implemented that should be traced with the new component.

To successfully complete this work, you should have:

• good HDL programming skills,
• experience with microcontroller programming,
• basic knowledge about Git,
• first experience with the Linux environment.

The student is expected to be highly motivated and independent.

Tracing of events in hardware components is one powerful tool to monitor, debug and improve existing designs. Through this approach detailed insights can be acquired and peak performance can be achieved, while being a challenging task to be integrated with good performance. One of the major challenges of tracing is to collect as much information as possible with ideally no impact on the to-be-analyzed system. Herewith, it can be ensured that the gained insights are representative of an execution without any tracing enabled. In this work, a hardware tracing component should be designed that takes an arbitrary data input and sends it via an ethernet connection to a different PC that performs the postprocessing of the data. The tracing component has to be designed in a way that for sending the data over ethernet no CPU involvement is required to minimize the impact on the traced system. This tracing component should be integrated into the hardware platform based on a Xilinx Zynq board. This features a heterogeneous ARM multicore setup directly integrated into the ASIC, combined with programmable logic in the FPGA part of the chip. In the FPGA a hardware accelerator is already implemented that should be traced with the new component.

To successfully complete this work, you should have:

• good HDL programming skills,
• experience with microcontroller programming,
• basic knowledge about Git,
• first experience with the Linux environment.

The student is expected to be highly motivated and independent.

Upcoming Ethernet networks carrying mixed-critical traffic, like automotive or industrial IoT networks, will be characterized by high amounts of fluctuating throughputs and workloads as well as a variety of different flow priorities. The efficient utilization of parallel processing ressources in the form of available compute nodes and CPU cores within a node, the differentiation between priorities, as well as the provision of adequate quality of service will be equally important. A recently developed load balancer design combines dynamic intra- and inter-node Receive-Side Scaling in hardware with priority-awareness to address these challanges. Its core functionality as well as an exemplary network for deployment have been modeled using a simulation framework in C++. The load balancer currently allows all flow priorities to be processed by every CPU core of a compute node, but shall be further refined to configurably steer selected flow priorities to a subset of CPU cores and to dynamically balance workloads within the configured pool of cores.

The goal of this bachelor thesis is to extend the current load balancer model in C++ to integrate the ability of pinning selected flow priorities to certain CPU cores within a compute node. The enhanced model shall be evaluated for a variety of different flow and core configurations with respect to the achievable end-to-end packet latency as well as the expected power consumption.

An upcoming trend in the development of compute architecture can be seen over the last few years. Next to the ever-increasing number of cores in one system, dedicated hardware accelerators for a specific task are getting increasingly widespread. These hardware accelerators are designed to outperform a general-purpose CPU resulting in a performance increase as well as a relief of the CPU. One challenging task for utilizing the accelerator efficiently is the implementation of a performant interface in addition to a way to notify the issuing task after completing the task in a hardware accelerator. The proof of concept for hardware accelerating this notification is accomplished by integrating the framework, software- as well as hardware-wise, into a heterogeneous architecture simulated in a full system simulation using Gem5. This work focuses on optimizing a hardware prototyping environment to further evaluate the hardware accelerator concepts not only via a simulation but also through a real hardware platform. The used hardware platform is a Xilinx Zynq board. This features a heterogeneous ARM multicore setup directly integrated into the ASIC, combined with programmable logic in the FPGA part of the chip. On the software side, a similar setup as in the simulation environment is used including the use of Linux as the operating system.

At LIS we want to use the Duckietown hardware and software ecosystem for experimenting with our reinforcement learning based learning classifier tables (LCT) as part of the control system of the Duckiebots: https://www.ce.cit.tum.de/lis/forschung/aktuelle-projekte/duckietown-lab/

More information on Duckietown can be found on https://www.duckietown.org/.

In this student work, we want to improve the overall image processing pipeline.
A first step is to analyse the image processing pipeline.
Afterwards the pipeline should be modified (adding, reordering stages) according to state of the art methods (literature research required) to improve the pipeline's accuracy.
Finally, the improvements should be measured and compared to before.

At LIS we want to use the Duckietown hardware and software ecosystem for experimenting with our reinforcement learning based learning classifier tables (LCT) as part of the control system of the Duckiebots: https://www.ce.cit.tum.de/lis/forschung/aktuelle-projekte/duckietown-lab/

More information on Duckietown can be found on https://www.duckietown.org/.

In this student work, we want to improve single stages of the image processing pipeline.
A first step is to analyse the image processing pipeline.
Afterwards the one with the biggest bottleneck in terms of functional accuracy or computation is selected to be optimized according to state of the art methods (literature research required).
Finally, the improvements should be measured and compared to before.

As computer networks, be it in the automotive, industrial or data center domain, become more complex over time and are challenged with higher amounts of traffic as well as more complex processing tasks, the development of new networking equipment is of high importance. Simulation frameworks, like the event-based network simulator OMNeT++, can be helpful in the fast and agile exploration of new design concepts for next generation networking hardware. In order to assess design improvements and enhancements of a recently developed load balancer design, also the expected power consumption of compute nodes in simulated networks will have to be evaluated.

To achieve this, the goal of this Bachelor Thesis is the development and evaluation of an extension to an existing simulation model for an automotive network which is incorporating a set of compute nodes and their internal design together with a load balancer. To this end, the existing model is planned to be modified in a way so that intervals can be determined when CPU cores are busy processing data packets and when they reside in idle mode. During phases of lower or no workload, a DVFS-like power consumption model can then be implemented where CPU cores scale down their clock frequency and supply voltage after configurable idle timeouts. During longer off-times also entering and leaving sleep states will be considered while integrating the necessary latencies to change power states. Finally, a power consumption trace can be generated out of the newly acquired simulation results.