Bachelorarbeiten

Static analysis plays an important role in understanding how software is expected to behave and in identifying potential defects early in the development process. While functional correctness can often be assessed statically, precise timing analysis is typically performed through dynamic methods, as execution time strongly depends on architectural features and shared hardware resources that influence temporal behavior.

Nevertheless, even when abstracting from certain dynamic effects—such as shared resource contention and detailed memory access behavior—it is possible to estimate the number of processor cycles required to execute a given sequence of instructions, provided that the target architecture is well understood. Hardware simulators such as Spike or gem5 follow this principle by modeling processor behavior to approximate execution timing.

The objective of this thesis is to develop a tool that estimates the cycle count required to execute specific instruction sequences on Infineon’s TriCore architecture. The focus will be on modeling the architectural pipelines, taking into account their structure, parallelism capabilities, and constraints. In particular, the work will analyze how different pipeline configurations influence instruction throughput and latency, as well as the benefits and limitations introduced by the multi-pipeline design.

Voraussetzungen

Modern MPSoC architectures are increasingly limited by off-chip memory latency. To mitigate this bottleneck, a page-based hardware preload unit has been developed that speculatively transfers DRAM pages upon last-level cache misses in order to hide memory access latency.

The goal of this bachelor thesis is to perform a systematic and scientifically sound evaluation of this architecture using internationally recognized embedded benchmark suites. The work will focus on identifying, porting, and executing suitable bare-metal benchmarks on an FPGA-based RISC-V platform (CVA6 architecture). Candidate benchmark suites include Embench, CoreMark, PolyBench/C, MiBench, and other memory-intensive workloads. The final selection will be made during the course of the thesis based on feasibility and relevance.

The thesis involves implementing the benchmarks in the existing hardware/software framework, conducting structured performance measurements, and comparing different system configurations (e.g., with and without the preload unit). Particular emphasis will be placed on analyzing memory behavior, working-set characteristics, and access patterns.

Beyond implementation, the thesis will provide a scientific evaluation of how different workload classes interact with page-based preloading. Results will be analyzed quantitatively and presented in a clear and reproducible manner using normalized speedups and workload classifications.
The outcome of this work will provide a solid experimental foundation for further research and potential publications in the area of memory-optimized MPSoC architectures.

Voraussetzungen

Page-based memory preloading typically relies on fixed burst lengths to transfer data efficiently from DRAM. While long bursts maximize preload throughput, they reduce responsiveness to demand-driven CPU memory accesses. Short bursts improve reactivity but underutilize available memory bandwidth.

This thesis builds on the existing page-based preload unit and investigates a hardware-based mechanism for dynamically adjusting preload burst length according to current memory system utilization. The goal is to balance preload efficiency and fast reaction to demand accesses at runtime. The proposed mechanism adapts burst length based on simple runtime indicators such as DRAM activity or the presence of competing CPU requests. The implementation extends the existing preload FSM and does not require any modifications to the CPU microarchitecture

Evaluation on an FPGA-based platform analyzes execution time, interference with demand accesses, and bandwidth utilization under different memory-intensive workloads. The results aim to demonstrate that adaptive burst sizing is an effective and low-overhead technique to improve the robustness of memory-side preloading.

Voraussetzungen

At LIS, we leverage the Duckietown hardware and software ecosystem to experiment with our reinforcement learning (RL) agents, known as learning classifier tables (LCTs), as part of the Duckiebot control system. More information on Duckietown can be found here.

In previous work, both the default PID controllers for steering and speed control were replaced independently by LCT RL agents. The modified versions of the Duckiebot control systems can keep up, respectively, with the default versions in terms of driving performance while using just slightly more computational resources. With some additional changes to the image processing pipeline, we also improved the accuracy of state measurements, e.g., the distance to the center of the lane. However, the two separate agents have not been combined so far, and have not been exposed to more complex driving scenarios.

This thesis aims to have the Duckiebots' driving be controlled entirely by RL. The student can achieve this by either merging our two RL agents into one or via a multi-agent approach. As their selected actions affect each other, they cannot be treated as entirely independent. For example, a more substantial heading angle correction is necessary to avoid leaving the lane when accelerating in curves.

The first step in this thesis will be to analyze the existing agents and investigate different concepts for their combination. When implementing the selected approach(es), new states and actions will likely extend the ruleset(s), which will demand more complex reward and Q-value update functions. Ideally, code optimizations will decrease the minimum possible RL cycle period. The student will compare the new system configuration to those with the existing separate agents and the baseline PID controller version regarding driving performance and computational resource utilization. A potential extension is the integration of more complex scenarios, such as intersections, pedestrian crossings, or traffic lights.

If the current LCT agents do not yield satisfactory results, the student could also explore other agent approaches, such as deep RL. As such methods are generally more resource-hungry, they might only be feasible by offloading parts of the control system to the Jetson Nano's GPU.

Voraussetzungen