PASSTA

Tracing of events in hardware components is one powerful tool to monitor, debug and improve existing designs. Through this approach detailed insights can be acquired and peak performance can be achieved, while being a challenging task to be integrated with good performance. One of the major challenges of tracing is to collect as much information as possible with ideally no impact on the to-be-analyzed system. Herewith, it can be ensured that the gained insights are representative of an execution without any tracing enabled. In this work, a hardware tracing component should be designed that takes an arbitrary data input and sends it via an ethernet connection to a different PC that performs the postprocessing of the data. The tracing component has to be designed in a way that for sending the data over ethernet no CPU involvement is required to minimize the impact on the traced system. This tracing component should be integrated into the hardware platform based on a Xilinx Zynq board. This features a heterogeneous ARM multicore setup directly integrated into the ASIC, combined with programmable logic in the FPGA part of the chip. In the FPGA a hardware accelerator is already implemented that should be traced with the new component.

To successfully complete this work, you should have:

• good HDL programming skills,
• experience with microcontroller programming,
• basic knowledge about Git,
• first experience with the Linux environment.

The student is expected to be highly motivated and independent.

With the ever-increasing network speeds of physical links, the processing of packets on network nodes is becoming more and more of a bottleneck. Packet processing on a standard Linux-based network node traditionally involves the operating system (OS). Since an OS is usually optimized for a range of tasks rather than a specific task, using conventional Linux kernel functionalities for packet processing can degrade performance. For this reason, approaches to bypass the kernel have been proposed to perform network processing in user space.

One approach of bypassing the kernel that has attracted growing interest in recent years is Data Plane Development Kit (DPDK). By processing packets entirely in user space, DPDK avoids time-consuming context switches between user space and kernel space. This comes at the cost of one CPU core actively polling for new packets, instead of the network interface card (NIC) triggering interrupts for incoming packets. In addition, DPDK itself mainly provides the poll mode drivers for selected NICs, but the processing of the packets is the duty of the application using DPDK. Thus, while DPDK is suitable for certain application scenarios, there are also numerous use cases that are better suited to be implemented using the Linux networking stack. For example, to establish a Transmission Control Protocol (TCP) connection, an additional user space TCP/IP stack must be implemented or taken from open-source projects. These are generally not as feature-rich as the conventional Linux networking stack and do not necessarily improve performance.

This work aims to find a method to compare applications using DPDK with applications using the Linux network stack. Envisioned is a client-server application that uses iperf3 to generate data traffic.

To successfully complete this work, you should have:

• very good programming skills in Python and C/C++,
• basic knowledge about Git,
• first experience with the Linux environment.

The student is expected to be highly motivated and independent.

An upcoming trend in the development of computer architecture can be seen over the last few years. Next to the ever-increasing number of cores in one system, dedicated hardware accelerators for specific tasks are getting increasingly widespread. On the software side, multithreaded applications are gaining more popularity as one approach to maximize the utilization of the underlying hardware architectures. Here Intra-/Inter-Process Communication (IPC) becomes more and more of a limiting factor in these systems. Besides the data transfer, primarily used in Inter-Process Communication, the notification can be a time-consuming operation in IPC mechanisms.

This work focuses on the epoll mechanism present in Linux. This mechanism can be attached to different file descriptors to be informed of whether a certain event occurred. In case no events are available the thread waits until events occur, which implies being notified by the thread that performs this event. Hence epoll is purely a notification mechanism that can be attached to different IPC mechanisms used to transfer data. This work should focus on eliminating/minimizing the cost of the notification by developing a hardware accelerator that relieves the threads from the notification. Here a solution is envisioned that improves the performance of the thread sending the notification as well as the one waiting for the events. The proof of concept should be accomplished by integrating the framework, software- as well as hardware-wise, into a heterogeneous architecture simulated in full system simulation using Gem5.

To achieve this task, the existing mechanism in Linux has to be analyzed. Therefore, microbenchmarks have to be developed to elaborate the time-consuming operations to be offloaded to hardware. This analysis should result in a concept to be integrated into the simulated system to show in the end the achievable performance improvement. Combined with the development, a related work analysis for existing similar approaches is part of this work.

To successfully complete this work, you should have:

• first experience with embedded programming,
• very good programming skills in Python and C/C++,
• basic knowledge about Git,
• first experience with the Linux environment.

The student is expected to be highly motivated and independent.

In this thesis, you lead the setup of the L4Re (L4 Runtime Environment) on Raspberry Pi devices. This is an exciting opportunity to work on cutting-edge technology, combining the flexibility of L4 microkernel architecture with the capabilities of Raspberry Pi to build secure and modular operating systems for embedded systems.

You will delve into the fascinating world of microkernel architecture. Unlike traditional monolithic kernels, where most functionality resides within the kernel, microkernels follow a minimalist approach. The microkernel serves as a lightweight core, providing only essential services such as interprocess communication (IPC) and memory management. Additional operating system services and functionalities, including device drivers and file systems, are implemented as separate user-level processes or servers that run outside the microkernel.

Responsibilities:

• Set up and configure the development environment for L4Re on Raspberry Pi, including toolchain and cross-compilation environment.
• Obtain the L4Re source code by downloading from the official repository or using a specific release.
• Build the L4Re system for Raspberry Pi, ensuring successful compilation and linking of components.
• Deploy the compiled L4Re system onto Raspberry Pi boards, including bootloader setup and configuration.
• Test and verify the functionality and performance of the L4Re system on Raspberry Pi, conducting both functional and security evaluations.
• Develop custom components and applications on top of L4Re, integrating them into the system and extending its functionality.
• Document the setup process, configurations, and customizations, ensuring clear and concise documentation for future reference.

• Solid understanding of embedded systems development and experience with low-level programming.
• Proficiency in C/C++ programming languages and familiarity with cross-compilation environments.
• Strong knowledge of operating system concepts and microkernel architectures, preferably with experience working with L4-based systems.
• Experience with Raspberry Pi development and configuration, including bootloader setup and deployment.
• Familiarity with embedded Linux, device drivers, and system-level software development.
• Excellent problem-solving skills and the ability to troubleshoot complex issues.

Next to the raw computational performance of an system on chip (SoC), the power consumption is an important trait. Especially in the mobile domain, where the efficiency of the SoC is critical, the power consumption of the whole system needs to be considered. Multiple factors contribute to the overall power consumption, such as activity/state of the CPU, memory accesses including cache misses and use of potential hardware acceleration.

In this work the power consumption of a SoC should be analyzed, herefor an gem5 simulation model exists.

The operating system is responsible for scheduling different threads and processes running in the system. Hereby, the goal of the operating system is to provide each thread a fair share of the underlying available compute resources. The Linux kernel includes a software scheduler which determines where and when each thread should run. This decision is critical for the performance of multi-threaded application where compute resources need to be efficiently shared among multiple threads. Furthermore, the time it takes to make this decision and to switch from one thread to another are critical performance parameters for any software scheduler.

For this project, the goal is to analyze the Linux Scheduler and determine how hardware acceleration can be supported. This can include replacing scheduling classes or offloading specific scheduling functions to a hardware accelerator. At the end of the project a concept for hardware acceleration for the Linux Scheduler should be presented. The project is divided into two subprojects. One part focuses on the regular scheduling functions which are called during the periodic scheduler calls in the Linux kernel, while the other takes a look at rescheduling functionalities through interrupts.

Evaluation and comparisons are to be done with the full system cycle accurate simulator GEM5. For this, an existing setup of an ARM architecture including various tracing options is available.