TAPES - Trace-based Architecture Performance Evaluation with SystemC


TAPES is a simulation based approach for assisting system designers in the evaluation of architectures early in the design flow. It allows to assess the execution performance of applications on a system architecture and thereby investigate the quality of the allocation, binding and scheduling decisions.

The evaluation possibilities of TAPES encompass performance relevant data like load values of architecture resources, end to and processing latencies or queue fill levels for identifying bottlenecks in the system architecture. Further on, TAPES also provides means to estimate system power consumption.


The two basic principles of TAPES are

  • Abstraction of the architecture resources as black boxes
  • Interaction of the resources via transactions (SystemC TLM)

As TAPES aims at performance evaluation on system level, the internal implementation of either HW or SW based architecture modules is disregarded. The internal functionality of architecture blocks is modeled in TAPES simply as latencies that correspond to the actual processing time of real hardware or software. Only the interaction with their periphery and its temporal sequence is considered.

On the other hand, shared resources especially the communication infrastructure are modeled in more detail, either with a timed or - if required - with a cycle accurate model. This allows to capture resolution of conflicting accesses and thus to gain insight into the dynamic behavior of the real system.

Therefore, the functionality of the TAPES system model is specified in so-called application traces, which are executed at simulation run-time. A trace is a sequence of an arbitrary number of trace primitives, which describes the behavior of an architecture block when executing a specific sub-function. It is an abstract representation of the module's activity that could be observed on its interfaces when the corresponding sub-function is executed on a real implementation. Trace primitives mainly denote either transactions or delays. Transactions initiate the execution of a particular trace in the target module and thus allow to model the interplay of the architecture resources. Each architecture module contains one trace per sub-function that is mapped onto it.

The figure shows an example for a CPU that makes several read and write operations interleaved with phases of internal processing.

For architecture exploration, the simulation model can easily modified by editing a system configuration file and the files with the application traces. These files determine all major system properties like allocated resources and their properties, binding / scheduling of the tasks and also the memory architecture. As there is no need to recompile the underlying SystemC simulation program, the fast modifiability and the abstraction of the system functionality enable short turnaround times.


  • High Simulation Performance
  • Short Turnaround times by
  • Yet Accurate Results


  • Model adaptation via configuration files (no recompilation required)
  • Configurable system properties: number/type of resources, properties of resources (clock frequency, bus width, ...
  • Mixed accuracy simulation (abstract timed / cycle accurate system bus)
  • Adaptability of system functionality via trace files
  • Flexible stimuli generator for Ethernet traffic
  • Flexible measurement possibilities (load values, queue sizes, latencies, system power consumption)
  • Automation of simulation (generation of set of curves for sensitivity analysis)
  • Extension available for simulating time variant systems
  • XML-based configuration file
  • Implemented with SystemC 2.0.1


  • 4/4
    Andreas Lankes, Thomas Wild, Johannes Zeppenfeld: System Level Simulation of Autonomic SoCs with TAPES. Architecture of Computing Systems (ARCS) (Lecture Notes in Computer Science 4934), Springer, 2008, 9-22 mehr… BibTeX Volltext ( DOI )
  • 3/4
    Andreas Lankes, Thomas Wild, Johannes Zeppenfeld: Power Estimation of Time Variant SoCs with TAPES. 10th EUROMICRO Conference on Digital System Design: Architectures, Methods, Tools (DSD 07), 2007 mehr… BibTeX
  • 2/4
    Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf: Performance Evaluation for System-on-Chip Architectures using Trace-based Transaction Level Simulation. Design Automation & Test in Europe (DATE), 2006 mehr… BibTeX
  • 1/4
    Thomas Wild, Andreas Herkersdorf, Gyoo-Yeong Lee: TAPES - Trace-based architecture performance evaluation with SystemC. Design Automation for Embedded Systems Volume 10 (Numbers 2-3, Special Issue on SystemC-based System Modeling, Verification and Synthesis), 2006, pp 157-179 mehr… BibTeX