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Implementation and Evaulation of Hardware Match-Action Tables on FPGA


With the advent of research on the next generation of
mobile communications 6G, we are engaged in exploring
architecture extensions for Smart Network Interface Cards
(SmartNICs). To enable adaptive, energy-efficient and
low-latency network interfaces, we are prototyping a
custom packet processing pipeline on FPGA-based NICs,
partially based on the open-nic project

Incoming packet flows should be differentiated and differently
processed, which is typically solved with match-action tables (MATs).
MATs match on a certain packet condition (e.g. packet header 5-tuple) and execute an according action (e.g. dropping, forwarding or modifying the packet). A recent Xilinx IP core implements MATs that can be programmed with P4, a programmable packet processing language gaining momentum in networking. The goal of this work is to investigate the implementation of MATs in hardware, integrate them into our current HDL design based on open-nic and test and evaluate the results.


  •     Programming skills in VHDL/Verilog and C (and Python)
  •     Practical experience with FPGA Design and Implementation
  •     Good Knowledge of computer networks, OSI layer model and protocols
  •     Preferably basic knowledge of P4 packet processing language


Marco Liess, M. Sc.

Tel.: +


Marco Liess

Duckietown Bring-Up


At LIS we want to use the Duckietown hardware and software ecosystem for experimenting with our reinforcement learning based learning classifier tables (LCT) as part of the control system of the Duckiebots: https://www.ce.cit.tum.de/lis/forschung/aktuelle-projekte/duckietown-lab/

More information on Duckietown can be found on https://www.duckietown.org/.

Towards this goal, we need a (followup) working student who is improving the current infrastructure.

Towards this goal, the following three major tasks are necessary:

  1. Developping an infrastructure to track and visualize measurement data of the platform (e.g. CPU utilization) as well as the executed application.
  2. During this task also the source and periodicity of already provided data should be analyzed.
  3. Setting up all Duckiebots incl. all their features and a pipeline to reflash them in case it's needed.
  4. FPGA-Extension: Searching for a concept, as well as implementing it.
  5. Final goal: demonstration of data exchange between NVIDIA Jetson and FPGA including protocol to specify the type of transfered data