Forschungspraxen / MSCE Research Internships

Einzelne angebotene Forschungspraxen oder MSCE Internships können auch als Aufgabe im Rahmen des Projektpraktikums Integrated Systems durchgeführt werden. Für die betreffenden Ausschreibungen ist dies im Ausschreibungstext explizit angegeben.

Offene Arbeiten

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Automotive Ethernet Anomaly Detection for Burst of Packets - ZCU102 Implementation

Beschreibung

Context:

Future cars have a wide variety of sensors, such as cameras, LiDARs, and RADARs that generate a large amount of data. This data has to be sent via an intra-vehicular network (IVN) to further processing nodes, and, ultimately, actuators have to react to the sensor input. In between the processing steps, the intra-vehicular network has to ensure that all of the data and control signals reach their destination in time. Hence, next to a large amount of data, there are also strict timing constraints that the intra-vehicular network has to cope with. Therefore, the so-called time-sensitive networking (TSN) has been introduced. The functional safety of such networks plays an important role against the background of highly automated driving. Emerging errors have to be detected early and potential countermeasures have to be taken to keep the vehicle in a safe state. Therefore, highly sophisticated monitoring and diagnosis algorithms are a key requirement for future cars. (See Project EMDRIVE)  

Our approach for such diagnosis builds on non-intrusively monitoring the intra-vehicular network by snooping on data traffic at an interconnect in the car. An analysis of the traffic shall give information about anomalies that occur inside the network as symptoms of an error inside the electrical architecture.   FORSCHUNGSPRAXIS:   The substance of this work is to first work into an existing design of an anomaly detection module that monitors individual packets in a flow. Based on the already existing work, several extensions have to be implemented (Verilog/SystemVerilog) in the hardware design to support anomaly detection in a burst of packet transfer. Type of the faults and anomalies:

  1. Arrival time of the Burst 
  2. Timing in-between packets in a single Burst
  3. Number of packets in a single Burst  

The system should be capable of detecting these fault classes and sending an alert/raising a flag to the software about the detected anomaly. It can then later on inject these types of fault classes during demonstration upon request.  The design should be simulated and implemented on an FPGA (ZCU102 Zync Board).  

If you are interested, feel free to contact me! Please send your CV as well as a recent transcript.

Voraussetzungen

The primary skills that will be developed and needed during this project are the following:

  • Proficiency in Verilog/SystemVerilog for FPGA design.
  • Ability to design and implement hardware modules.
  • Experience with FPGA simulation tools (e.g., ModelSim).
  • A strong background in System-on-Chip design.
  • A good understanding of network protocols and their implementation on FPGA platforms

Kontakt

zafer.attal@tum.de

Betreuer:

Zafer Attal

Laufende Arbeiten

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