Setting up L4Re on Raspberry Pi
Beschreibung
In this thesis, you lead the setup of the L4Re (L4 Runtime Environment) on Raspberry Pi devices. This is an exciting opportunity to work on cutting-edge technology, combining the flexibility of L4 microkernel architecture with the capabilities of Raspberry Pi to build secure and modular operating systems for embedded systems.
You will delve into the fascinating world of microkernel architecture. Unlike traditional monolithic kernels, where most functionality resides within the kernel, microkernels follow a minimalist approach. The microkernel serves as a lightweight core, providing only essential services such as interprocess communication (IPC) and memory management. Additional operating system services and functionalities, including device drivers and file systems, are implemented as separate user-level processes or servers that run outside the microkernel.
Responsibilities:
- Set up and configure the development environment for L4Re on Raspberry Pi, including toolchain and cross-compilation environment.
- Obtain the L4Re source code by downloading from the official repository or using a specific release.
- Build the L4Re system for Raspberry Pi, ensuring successful compilation and linking of components.
- Deploy the compiled L4Re system onto Raspberry Pi boards, including bootloader setup and configuration.
- Test and verify the functionality and performance of the L4Re system on Raspberry Pi, conducting both functional and security evaluations.
- Develop custom components and applications on top of L4Re, integrating them into the system and extending its functionality.
- Document the setup process, configurations, and customizations, ensuring clear and concise documentation for future reference.
Voraussetzungen
- Solid understanding of embedded systems development and experience with low-level programming.
- Proficiency in C/C++ programming languages and familiarity with cross-compilation environments.
- Strong knowledge of operating system concepts and microkernel architectures, preferably with experience working with L4-based systems.
- Experience with Raspberry Pi development and configuration, including bootloader setup and deployment.
- Familiarity with embedded Linux, device drivers, and system-level software development.
- Excellent problem-solving skills and the ability to troubleshoot complex issues.
Betreuer:
SystemC Model for Memory Preloading
Beschreibung
Since DRAM typically come with much higher access latencies than SRAM, many approaches to reduce DRAM latencies have already been explored, such as Caching, Access predictors, Row-buffers etc.
In the CeCaS research project, we plan to employ an additional mechanism, in detail a preloading mechanism of a certain fraction of the DRAM content to a small on-chip SRAM buffer. Thus, it is required to predict potentially next-accessed Cachelines, preload them to the SRAM and answer subsequent memory requests of this data from the SRAM instead forwarding them to the DRAM itself.
This functionality should be implemented as a TLM/SystemC model using Synopsys Platform Architect. A baseline system will bw provided, the goal is to implement this functionality in its simplest form as a baseline. Depending on the progress, this can be extended or refined in subsequent steps.
A close supervision, especially during the inital phase, will be guaranteed. Nevertheless, some experience with TLM modelling (e.g. SystemC Lab of LIS) or C++ programming is required.
Voraussetzungen
- Experience with TLM modelling (e.g. SystemC Lab of LIS)
- B.Sc. in Electrical Engineering or similar
Betreuer:
Duckietown - Computer Vision Based Measurements for Performance Analyzes
Beschreibung
At LIS, we want to use the Duckietown hardware and software ecosystem for experimenting with our reinforcement learning based learning classifier tables (LCTs) as part of the control system of the Duckiebots: https://www.ce.cit.tum.de/lis/forschung/aktuelle-projekte/duckietown-lab/
More information on Duckietown can be found on https://www.duckietown.org/.
Currently, we are developing the infrastructure for our LCT experiments.
While several students are improving on the autonomous driving abilities of the Duckiebots, this work's goal is to develop a system which provides insights into the bots' driving performance.
Therefore, we need objective measurements by a third party which allow us to compare the driving performance (average speed, deviation from optimal line, …) between bots which might run different SW.
To compare specific scenarios, these measurements shouldn't only be a time series, but be enhanced by the position of the respective bot at this point in time. Similar to the modern sports apps: https://www.outdooractive.com/de/route/wanderung/tegernsee-schliersee/auf-dem-prinzenweg-vom-schliersee-an-den-tegernsee/1374189/#dm=1.
Towards this goal it's required to develop a camera-based mechanism, which identifies bots in the field, extracts their concrete position and calculates certain metrics like direction, velocity, on / off lane, spinning, deviation from ideal line, ….
This data then should be logged to be analyzed + visualized later.
Depending on the type of work (BA/FP vs MA) this work might include to enhance these measurements with internal data of the bots to compare internal and external perception, and to develop tools for easy analysis.
Voraussetzungen
- independent work style
- problem solving skills
- computer vision knowledge (openCV)
- programming skills (we are open which framework is used - Python, C++ (Qt), Matlab, ...
- Linux basics (permissions)
Kontakt
flo.maurer@tum.de
Betreuer:
Bring-up and Evaluation of FPGA Network Accelerator Boards
Beschreibung
With the advent of research on the next generation of
mobile communications 6G, LIS is engaged in exploring
architectures and architecture extensions for networking
hardware. In order to research on energy-efficient and
low-latency network interfaces for next-generation
networks, we are setting up a hardware testbed with
FPGA-based Network Interface Accelerator Cards in the
form of Xilinx Alveo and NetFPGA SUME FPGA boards.
This requires the bring-up and evaluation of the HDL
Design, the Linux kernel drivers and applications.
OpenNIC provides open-source code for an HDL design and kernel driver as basis for a custom hardware network interface on FPGAs. The goal of this work is to configure and setup the project on the available hardware resources at our chair. This includes analyzing the open-source designs, establishing a workflow to modify given designs with proper hardware and software design tools, documentation and integration and testing the correct functionality of both hardware and software. As an additional task, the setup could be evaluated concerning key performance indicators (KPIs) such as latency, bandwidth, memory footprint, etc. This can also involve the creation of custom tests in (both) hardware and software.
Voraussetzungen
- Good experience with Linux, Command Line Tools and Bash scripting
- Programming skills in VHDL/Verilog and C (and Python)
- Preferably experience with FPGA Design and Implementation
Kontakt
Betreuer:
XCS with dynamic sized experience replay
XCS, Experience replay, machine learning, reinforcement learning, genetic algorithms
Beschreibung
XCS is a class of human-interpretable machine learning algorithm which combines the concepts of machine learning from reinforcement learning and the pattern recognition property of genetic algorithms. XCS operates my maintaining a population of classifiers. Experience replay is a popular strategy used in machine learning to speed the process of learning and improve performance.
In this work, you will
1. Understand the XCS algrorithm and its implementation in python.
2. Implement dynamic sized ER buffer for the XCS.
3. Experiment your work on various benchmarks used in the machine learning domain.
4. Compare your results against an XCS without ER and an XCS with fixed size ER.
Voraussetzungen
To successfully complete this project, you should already have the following skills and experiences:
- Good python skills
- Basic knowledge of machine learning
- Self-motivated and structured work style
Kontakt
Anmol Surhonne
Technische Universität München
Department of Electrical and Computer Engineering
Chair of Integrated Systems
Arcisstr. 21
80290 München
Germany
Phone: +49.89.289.23872
Fax: +49.89.289.28323
Building: N1 (Theresienstr. 90)
Room: N2137
Email: anmol.surhonne at tum dot de
Betreuer:
Implement a Neural Network based DVFS controller for runtime SoC performance-power optimization
Neural Networks, DVFS, Machine learning,
Beschreibung
Reinforcement learning (RL) has been widely used for run-time management on multi-core processors. RL-based controllers can adapt to varying emerging workloads, system goals, constraints and environment changes by learning from their experiences.
Neural Networks are a set of ML methods which are inspired by the human brain, mimicking the way that biological neurons signal to one another.
In this work, you will
1. Understand the working of Neural Networks. Implement a neural network in C.
2. Understand the architecture of the Leon3 based SoC.
3. Use neural networks to learn and control the processor voltage and frequency in runtime to optimize performance and power.
4. Design, test and implement the work on Xilinx FPGA
Voraussetzungen
To successfully complete this project, you should already have the following skills and experiences:
• Good VHDL and C programming skills
• Good understanding of MPSoCs
• Self-motivated and structured work style
• Knowledge of machine learning algorithms
Kontakt
Anmol Surhonne
Technische Universität München
Department of Electrical and Computer Engineering
Chair of Integrated Systems
Arcisstr. 21
80290 München
Germany
Phone: +49.89.289.23872
Fax: +49.89.289.28323
Building: N1 (Theresienstr. 90)
Room: N2137
Email: anmol.surhonne at tum dot de
Betreuer:
Simulation of In-Vehicular-Network
Beschreibung
Context:
Future cars have a wide variety of sensors such as cameras, LiDARs and RADARs that generate a large amount of data. This data has to be sent via an intra-vehicular network (IVN) to further processing nodes and, ultimately, actuators have to react to the sensor input. Inbetween the processing steps the intra-vehicular network has to ensure that all of the data and control signals reach their destination in time. Hence, next to a large amount of data, there are also strict timing constraints that the intra-vehicular network has to cope with. Therefore, the so called time-sensitive networking (TSN) has been introduced. The functional safety of such networks plays an important role against the background of higly automated driving. Emerging errors have to be detected early and potential countermeasures have to be taken to keep the vehicle in a safe state. Therefore, highly sophisticated monitoring and diagnosis algorithms are a key requirement for future cars. (See Project EMDRIVE)
Our approach for such diagnosis builds on non-intrusively monitoring the intra-vehicular network by snooping on data traffic at an interconnect in the car. An analysis of the traffic shall give information about anomalies that occur inside the network as symptoms of an error inside the electrical architecture.
THIS WORK:
Substance of this work is to first work into an existing simulation environment for an IVN with TSN in OMNET++. Based on the already existing work, several extensions have to be implemented (C++ based) in the simulation environment to mimic certain fault classes like delayed messages, broken links, etc. These fault classes can then later on be injected into the IVN simulation. (FP or IDP)
It is desired to combine Forschungspraxis and Master thesis in the context of this project. In this way, the time during Forschungspraxis can be used to familiarize with the OMNET++ simulation environment.
Voraussetzungen
OSI-Layer
Basic knowledge in C++
Basic knowledge in simulations
Kontakt
matthias.ernst@tum.de
Betreuer:
AI based Automotive Ethernet Anomaly Detection
Beschreibung
CONTEXT:
Future cars have a wide variety of sensors such as cameras, LiDARs and RADARs that generate a large amount of data. This data has to be sent via an intra-vehicular network (IVN) to further processing nodes and, ultimately, actuators have to react to the sensor input. Inbetween the processing steps the intra-vehicular network has to ensure that all of the data and control signals reach their destination in time. Hence, next to a large amount of data, there are also strict timing constraints that the intra-vehicular network has to cope with. Therefore, the so called time-sensitive networking (TSN) has been introduced. The functional safety of such networks plays an important role against the background of higly automated driving. Emerging errors have to be detected early and potential countermeasures have to be taken to keep the vehicle in a safe state. Therefore, highly sophisticated monitoring and diagnosis algorithms are a key requirement for future cars. (See Project EMDRIVE)
Our approach for such diagnosis builds on non-intrusively monitoring the intra-vehicular network by snooping on data traffic at an interconnect in the car. An analysis of the traffic shall give information about anomalies that occur inside the network as symptoms of an error inside the electrical architecture.
FORSCHUNGSPRAXIS:
Substance of this work is to first work into an existing simulation environment for an IVN with TSN in OMNET++. Based on the already existing work, several extensions have to be implemented (C++ based) in the simulation environment to mimic certain fault classes like delayed messages, broken links, etc. These fault classes can then later on be injected into the IVN simulation. (FP or IDP)
MASTERARBEIT:
Subsequently, the IVN simulation can be used to generate a stream of Ethernet traffic that can be investigated for aforementioned anomalous behavior. The challenge is to detect and classify anomalous behavior without any preknowledge on timing and nature of the same. Therefore, several methods can be applied, ranging from static measurement methods to AI based anomaly detection. The focus of this work could lie on the application of LSTM or transformer-based models. The preferred development environment builds on python and related libraries like TensorFlow and Keras. Comparing at least two different anomaly detection methods and exploring, as well as discussing their respective advantages rounds up the master thesis. (M)
It is desired to combine Forschungspraxis and Master thesis in the context of this project. In this way, the time during Forschungspraxis can be used to familiarize with the OMNET++ simulation environment.
If you are interested, feel free to contact me! Please send your CV as well as a recent transcript.
Voraussetzungen
In the course of both projects (FP+MA) it is possible to take enough time to work into the related technichal fields. The main skills that will be developed and needed during this project are the following:
OSI-Layer,
Basics in automotive E/E architectures,
Basics in simulations (OMNET++)
Basics in C++ and Python
Experience with AI (TensorFlow and Keras)
Kontakt
matthias.ernst@tum.de
Betreuer:
Porting of HDL Designs for Packet Processing to new FPGA board
Beschreibung
In order to research on energy-efficient and
low-latency network nodes for next-generation
networks, we are setting up a hardware testbed
with FPGA-based Network Interface Accelerator
Cards in the form of Xilinx Alveo FPGA boards.
Previous research in the area of Network Interface
Cards (NICs) at our chair led to HDL Designs of
Packet Processing Pipelines on older generation
FPGAs, which shall serve as basis for further research on Xilinx Alveo FPGA boards.
Therefore, the goal of this work is to port these existing HDL Designs to the new FPGAs. This includes analyzing the existing designs, extracting the required logic and integrating it into the OpenNIC framework. Further, the functionality of the designs has to be verified by testing.
Voraussetzungen
- Experience with Linux, Command Line Tools and Bash scripting
- Programming skills in VHDL/Verilog and C (and Python)
- Experience with FPGA Design and Implementation
Kontakt
Marco Liess, M.Sc.
Tel.: +49.89.289.23873
Gebäude: N1 (Theresienstr. 90)
Raum: N2139
Email: marco.liess@tum.de