Forschungspraxen / MSCE Research Internships

Background

Modern networked systems increasingly rely on virtualization, indirection, and pooled accelerator resources to improve scalability and resource utilization. In emerging DPU- or SmartNICbased pooling architectures, processing a packet may require access to, or updates of, flow-, connection-, or protocol-related context maintained by other DPUs. For example, a packet may arrive at one DPU or SmartNIC, while the relevant state context for the corresponding flow or connection may reside on another DPU.

This breaks the traditional assumption that packet arrival and packet processing naturally happen at the same location. In a distributed processing environment, the arrival location of each packet is not automatically known to all relevant processing entities. Therefore, the system needs an efficient mechanism to inform the responsible DPUs where packets have arrived.

In the context of distributed packet processing, this issue becomes especially important for single-flow processing, where packets belonging to the same flow may require ordered processing, shared state access, or state synchronization across multiple DPUs.

Objective

The objective of this FP is to design and evaluate an efficient packet arrival-location resolution mechanism for distributed DPU/SmartNIC-based packet processing.

A straightforward solution is to broadcast or multicast the arrival information of every packet to all relevant DPUs. However, this approach can consume a large amount of interconnect bandwidth, especially under high packet rates or larger DPU pools. Therefore, this project aims to develop a more scalable mechanism with lower communication overhead.

The student is expected to analyze the limitations of baseline approaches, identify the key design trade-offs, and propose an improved arrival-location resolution scheme. The proposed scheme should be evaluated with respect to notification latency, bandwidth consumption, metadata or storage overhead, and scalability.

Evaluation

The proposed solution will be evaluated in comparison with the baseline models.

If a suitable gem5-based simulation model is available in time, the mechanisms may be implemented and evaluated in C++ within the gem5 simulation environment. Otherwise, the student will build an event-driven timing-level simulation model in Python.

The main evaluation metrics include:

• Arrival-location notification latency: the time between the physical arrival of a packet at one DPU and the moment when the relevant target DPU or target DPU group becomes aware of the packet’s arrival location.
• Inter-DPU bandwidth consumption: the amount of communication traffic introduced by the discovery or advertising mechanism.
• Metadata or storage overhead: the number of bits required per packet, flow, table entry, or local arrival-location table, depending on the mechanism.
• Scalability: the behavior of the mechanism as the number of DPUs in the target DPU group increases, for example from 2 to 8 DPUs.

Although the student may seek inspiration from general distributed systems, where problem occur as: when work arrives at one node but may need the context on another node, the system must efficiently advertise or discover the arrival location while avoiding excessive communication overhead, the arrival-location resolution mechanism should be evaluated with a simplified pipelinebased packet-processing model, rather than in a stand-alone general distributed processing scenario. In addition, the evaluation should discuss how arrival-location resolution affects packet-processing progress.

Baseline Models

The project should compare the proposed mechanism against the following baseline or reference models.

1. Broadcast or Multicast upon Every Packet Arrival: In this baseline, whenever a packet arrives at a DPU, the arrival information is broadcast or multicast to all relevant DPUs. This approach is simple and ensures that all DPUs can learn the packet arrival location, but it may introduce significant bandwidth overhead.
2. Timely Advertising: In this model, several advertising strategies are combined with a local arrival-location table. The table records where packets have arrived and allows responsible DPUs to advertise packet arrival in a timely manner. Further details of this model will be provided by the supervisor during the project. The student is expected to implement, compare, and discuss these models with respect to their notification latency, bandwidth consumption, metadata/storage overhead, and scalability.

Voraussetzungen

Modern compute architectures increasingly rely on heterogeneous systems that combine general-purpose CPUs with dedicated hardware accelerators. These accelerators offer significant performance benefits and reduce CPU load, but require efficient interfaces and notification mechanisms to be fully effective. A proof-of-concept for hardware-assisted task notification has already been implemented and evaluated in a full-system simulation using Gem5.

This work builds on the existing framework and focuses on improving a hardware prototyping environment to evaluate these concepts on a real platform. The target system is an Xilinx Zynq board that integrates ARM multicore processors with FPGA-based programmable logic and runs a Linux-based software stack.

The main objective is to optimize the resources of an existing hardware unit. This includes analyzing resource usage (e.g., LUTs, BRAM, DSPs) and performance, identifying inefficiencies, and applying optimizations at the RTL and system level. The optimized design will be implemented and evaluated on the FPGA, with results compared to the baseline.

Tasks include:

• Analyzing the existing hardware design and identifying bottlenecks
• Implementing and validating resource optimizations
• Testing on the FPGA platform and evaluating results
• Documenting the work and findings

Voraussetzungen

Im Rahmen dieser Forschungspraxis soll ein Ethernet-basiertes Kommunikationsmodul zur effizienten Übertragung von Laufzeit- und Performance-Daten aus einem FPGA-System entwickelt und integriert werden. Ziel ist es, einen bestehenden Hardware-Prototyp um eine leistungsfähige, nicht-intrusive Streaming-Schnittstelle zu erweitern, die eine kontinuierliche Analyse des Systemverhaltens während der Ausführung ermöglicht.

Kern der Arbeit ist die Integration eines 1G-Ethernet IP-Cores in das FPGA-Board Xilinx VCU118. Aufbauend darauf soll eine stabile Punkt-zu-Punkt-Verbindung zwischen dem FPGA und einem Host-PC realisiert werden. Die Datenübertragung erfolgt paketbasiert über Ethernet und dient der Ausleitung von Metriken, die innerhalb des Systems generiert werden.

Die zu übertragenden Daten bestehen aus einer Menge konfigurierbarer Performance-Metriken mit unterschiedlicher Bitbreite. Diese werden über eine FIFO-Schnittstelle an das Ethernet-Modul übergeben. Als Datenquellen dienen dabei sowohl eine AXI-basierte Traffic-Analyseeinheit als auch Performance Counter der bestehenden Preload-Unit.

Neben der Hardwareentwicklung umfasst die Arbeit auch die Anpassung und Erweiterung einer bestehenden Python-basierten GUI auf dem Host-PC. Diese dient zur Visualisierung und Analyse der empfangenen Daten in Echtzeit. Die Schnittstelle zwischen Hardware und Software soll dabei so gestaltet werden, dass eine einfache Integration neuer Metriken möglich ist.

Voraussetzungen

Hardware prefetching is a technique used in modern processors to reduce memory access latency by predicting future data accesses and fetching data into the cache before it is explicitly requested by the processor. By exploiting regular access patterns, such as strided memory accesses, prefetchers can improve cache hit rate and overall system performance. 

This research internship focuses on the implementation of hardware prefetchers in modern processor cache systems. The intern will study the design and interfaces of HPDcache, which is already integrated into the CVA6 SoC. Based on this understanding, the intern will design and implement an IP-stride prefetcher and connect it to the HPDcache. The work also includes evaluating the implemented prefetcher using existing benchmarks on the FPGA board.

Through this internship, the student will gain hands-on experience in computer architecture, cache subsystem design, hardware integration, and experimental evaluation of prefetching techniques.

Voraussetzungen

At LIS, we use the Duckietown hardware and software ecosystem to investigate autonomous driving algorithms and reinforcement learning agents on Duckiebots, which are powered by NVIDIA Jetson Nano boards and drive autonomously on a miniature road network in our lab. More information on Duckietown can be found here.

The current perception pipeline consists of classical image-processing-based lane detection for steering and speed control and a CNN-based object detector (YOLOv8) for obstacles and traffic signs, already pushing the on-board hardware to its limits.

In this project, the goal is to redesign lane detection as a split-computing convolutional neural network that runs partially on the Duckiebot and partially on an external server, in order to improve utilization of the Jetson’s CPU and GPU while maintaining a framerate of about 30 Hz end-to-end. A lightweight lane or line detection network head should operate on raw camera images on the robot and output a compact intermediate representation that is sent over the network to a server for more computationally intensive processing, whose results are then used for vehicle control.

The student will first perform a literature review on efficient lane and line detection architectures (e.g., pixel-based, grid-based, anchor/curve-based, and keypoint-based networks, as well as Mobile LSD and related approaches) and select one or a small set of promising candidates. These models will be implemented in a split computing manner across Duckiebot and server, including the design of an appropriate split point, communication protocol, and integration into the existing control pipeline.?

A key part of the work is to systematically evaluate the trade-offs between model complexity, communication bandwidth, CPU/GPU utilization, and control performance, ensuring that the new system does not (significantly) increase latency or CPU load compared to the current classical lane detector. With an alleviated CPU utilization, we will enable the development of more complex Duckiebot behavior, such as safe navigation on tracks that include intersections, pedestrian crossings, and traffic lights, which has so far been infeasible due to the limited computational resources of the Jetson Nano. Furthermore, after developing the lane detection CNN, potential points of intersection with the object detection CNN can be analyzed for future partial combination.

Voraussetzungen

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