CeCaS

Im Rahmen dieser Forschungspraxis soll ein Ethernet-basiertes Kommunikationsmodul zur effizienten Übertragung von Laufzeit- und Performance-Daten aus einem FPGA-System entwickelt und integriert werden. Ziel ist es, einen bestehenden Hardware-Prototyp um eine leistungsfähige, nicht-intrusive Streaming-Schnittstelle zu erweitern, die eine kontinuierliche Analyse des Systemverhaltens während der Ausführung ermöglicht.

Kern der Arbeit ist die Integration eines 1G-Ethernet IP-Cores in das FPGA-Board Xilinx VCU118. Aufbauend darauf soll eine stabile Punkt-zu-Punkt-Verbindung zwischen dem FPGA und einem Host-PC realisiert werden. Die Datenübertragung erfolgt paketbasiert über Ethernet und dient der Ausleitung von Metriken, die innerhalb des Systems generiert werden.

Die zu übertragenden Daten bestehen aus einer Menge konfigurierbarer Performance-Metriken mit unterschiedlicher Bitbreite. Diese werden über eine FIFO-Schnittstelle an das Ethernet-Modul übergeben. Als Datenquellen dienen dabei sowohl eine AXI-basierte Traffic-Analyseeinheit als auch Performance Counter der bestehenden Preload-Unit.

Neben der Hardwareentwicklung umfasst die Arbeit auch die Anpassung und Erweiterung einer bestehenden Python-basierten GUI auf dem Host-PC. Diese dient zur Visualisierung und Analyse der empfangenen Daten in Echtzeit. Die Schnittstelle zwischen Hardware und Software soll dabei so gestaltet werden, dass eine einfache Integration neuer Metriken möglich ist.

Voraussetzungen

Modern MPSoC architectures increasingly suffer from memory access latency, particularly for workloads with predictable page-level access patterns.
This thesis builds upon an existing page-based hardware preload unit that operates at the interface between the last-level cache and the DRAM controller. The baseline design incrementally preloads pages only after a first demand miss has been observed, prioritizing pages based on spatial and temporal locality.

The goal of this work is to extend the existing preload unit with pattern-aware, speculative preloading capabilities. By observing memory access sequences in hardware, the preload unit shall identify recurring access patterns (e.g., linear or strided page traversal) and extrapolate future page candidates that have not yet been accessed by the processor. These predicted pages are inserted into the existing page queue with controlled priority, enabling preloading to begin earlier than in the purely reactive baseline design.

A central question is how well a single extrapolation mechanism can cope with access behaviours of differing regularity, ranging from the largely sequential traversal typical of instruction pages to sparser data-side patterns. One candidate to be investigated is a lightweight probabilistic model, such as a bounded Markov predictor over recently observed page transitions, whose prediction confidence governs the priority with which extrapolated pages enter the existing page queue. If the scope of the work permits, tracking access sequences separately per core shall be examined as an extension, with core identifiers forwarded via the AXI interconnect.

The extended design will be evaluated on the existing FPGA-based RISC-V prototype using memory-intensive workloads and microbenchmarks, quantifying performance improvements, extrapolation accuracy, and the impact of speculation on bandwidth utilization.

Voraussetzungen

Hardware prefetching is a technique used in modern processors to reduce memory access latency by predicting future data accesses and fetching data into the cache before it is explicitly requested by the processor. By exploiting regular access patterns, such as strided memory accesses, prefetchers can improve cache hit rate and overall system performance. 

This research internship focuses on the implementation of hardware prefetchers in modern processor cache systems. The intern will study the design and interfaces of HPDcache, which is already integrated into the CVA6 SoC. Based on this understanding, the intern will design and implement an IP-stride prefetcher and connect it to the HPDcache. The work also includes evaluating the implemented prefetcher using existing benchmarks on the FPGA board.

Through this internship, the student will gain hands-on experience in computer architecture, cache subsystem design, hardware integration, and experimental evaluation of prefetching techniques.

Voraussetzungen

Hardware preloading mechanisms, as investigated in the current project, must balance latency hiding against bandwidth efficiency. While page-based preloading can effectively amortize memory access latency, it may also lead to unnecessary bandwidth consumption when memory access patterns change dynamically. This thesis builds upon an existing page-based preload unit that incrementally transfers memory pages. The current baseline design employs fixed policies for page switching and preload completion, independent of the observed usefulness of partially loaded pages.

The objective of this work is to enhance the preload unit with self-adaptive control mechanisms that dynamically adjust preloading behavior based on runtime feedback. In particular, the preload unit shall monitor the usefulness of partially preloaded pages, enabling early termination of preload operations when further progress is unlikely to produce additional cache hits. Furthermore, the student will extend the page switching logic to consider multiple factors, including page priority, observed reuse, preload progress, and interruption frequency.

Experimental observations indicate that pages suspended due to page switching are often not accessed again in the future, raising the question under which conditions such pages should remain in the priority queue for continued preloading. In addition, the thesis will investigate more advanced priority strategies that augment the existing temporal and spatial locality scheme with runtime feedback and observed memory behavior.

All proposed strategies shall be developed and evaluated using RTL-based simulation as well as FPGA-based implementations. The overall goal of this thesis is to derive a self-adaptive and enhanced version of the existing preload unit. The enhanced design will be evaluated using synthetic microbenchmarks and representative benchmarks. The evaluation will quantify improvements in bandwidth efficiency and preload effectiveness under varying memory access characteristics.

Voraussetzungen