Klajd Zyla, M.Sc.

Switches and network interface cards receive traffic at hundreds of Gbit/s and process packets with stringent latency requirements. The bandwidth and forwarding latency of the interconnect highly affects the performance of the whole design. The goal of this seminar work is to investigate and compare state-of-the-art interconnects in terms of metrics such as throughput, latency, priority-awareness, scalability and chip area.

[1] Kurth, Andreas, et al. "An open-source platform for high-performance non-coherent on-chip communication." IEEE Transactions on Computers 71.8 (2021): 1794-1809.

[2] Lin, Jiaxin, et al. "PANIC: A high-performance programmable NIC for multi-tenant networks." Proceedings of the 14th USENIX Conference on Operating Systems Design and Implementation. 2020.

Switches and network interface cards receive traffic at hundreds of Gbit/s and process packets with stringent latency requirements. The bandwidth and forwarding latency of the interconnect highly affects the performance of the whole design. The goal of this seminar work is to investigate and compare state-of-the-art interconnects in terms of metrics such as throughput, latency, priority-awareness, scalability and chip area.

[1] Kurth, Andreas, et al. "An open-source platform for high-performance non-coherent on-chip communication." IEEE Transactions on Computers 71.8 (2021): 1794-1809.

[2] Lin, Jiaxin, et al. "PANIC: A high-performance programmable NIC for multi-tenant networks." Proceedings of the 14th USENIX Conference on Operating Systems Design and Implementation. 2020.

FlexRoute is a packet-processing architecture where offloads are arranged sequentially in the order that they are intended to be used. Each offload contains two forwarding channels in order to enable recirculation of packets through the sequence of offloads even when packets are coming back to back. It also consists of flexible forwarding logic that bypasses the corresponding processing units if their functionality is not needed by an incoming packet in order to reduce latency. Furthermore, it contains a scheduler that steers traffic to the least loaded processing unit and priority-aware traffic arbiters that privilege high-priority packets when traffic from multiple sources needs to exit the offload.

We have shown the potential benefit of our proposed design via cycle-accurate register-transfer level (RTL) simulations in Xilinx Vivado. The goal of this project is to synthesize and implement the design on an FPGA by using Vivado. Moreover, the design should be tested by injecting network traffic via Ethernet and measuring the throughput and the per-packet latency.

• Good knowledge of the basics of digital circuits, especially regarding timing analysis
• Experience with hardware description languages (HDL), such as VHDL or Verilog
• Preferably experience with electronic design automation (EDA) tools, such as Xilinx Vivado

Switches and network interface cards receive traffic at hundreds of Gbit/s and process packets with stringent latency requirements. The bandwidth and forwarding latency of the interconnect highly affects the performance of the whole design. The goal of this seminar work is to investigate and compare state-of-the-art interconnects in terms of metrics such as throughput, latency, priority-awareness, scalability and chip area.

[1] Kurth, Andreas, et al. "An open-source platform for high-performance non-coherent on-chip communication." IEEE Transactions on Computers 71.8 (2021): 1794-1809.

[2] Lin, Jiaxin, et al. "PANIC: A high-performance programmable NIC for multi-tenant networks." Proceedings of the 14th USENIX Conference on Operating Systems Design and Implementation. 2020.