6G-life

With the advent of research on the next generation of mobile communications 6G, LIS is engaged in exploring architectures and architecture extensions for networking hardware. In order to research on energy-efficient and low-latency network interfaces for next-generation networks, we are setting up a hardware testbed with FPGA-based Network Interface Accelerator Cards and AMD Epyc and Ryzen Processors.

The incoming traffic load and with it the computing requirements on network processing nodes such as edge servers can span multiple magnitudes in a matter of milliseconds and less. The systems are ususally dimensioned to cope with peak loads, resulting in a low resource utilization when traffic is little. To ensure a highly energy-efficient resource utilization, dynamic power management with respect to fluctuating processing requirements is necessary to reduce the power consumption (e.g. by dynamic voltage frequency scaling (DVFS) or power gating) in times of low traffic load.

The goal of this work is to explore Linux power management possibilities on AMD processors. This involves researching possible power management options (e.g. DVFS) in Linux, understanding and using the provided API, verifying the correct functionality and setting up a framework for measurement and benchmarking. The measurements shall be processed and evaluated concerning key performance indicators like power consumption, switching delay, etc.

• Good experience with Linux, Command Line Tools and Bash scripting
• Programming skills in C and Python
• Preferably practical experience with the Linux Kernel, Kernel tracing functionality and low-level software
• Solid understanding of operating system concepts and hardware/software interactions

With the advent of research on the next generation of
mobile communications 6G, LIS is engaged in exploring
architectures and architecture extensions for networking
hardware. In order to research on energy-efficient and
low-latency network interfaces for next-generation
networks, we are setting up a hardware testbed with
FPGA-based Network Interface Accelerator Cards in the
form of Xilinx Alveo and NetFPGA SUME FPGA boards.
This requires the bring-up and evaluation of the  HDL
Design, the Linux kernel drivers and applications.

OpenNIC provides open-source code for an HDL design and kernel driver as basis for a custom hardware network interface on FPGAs. The goal of this work is to setup the Linux DPDK driver to interface with the HDL design on the FPGA, validate the communication with the FPGA and correct functionality of the driver and finally evaluate the driver, especially with comparison to the standard Linux network driver. This can involve establishing a test setup with additional postprocessing regarding key performance indicators (KPIs) such as latency, bandwidth, memory footprint, etc., and tracing of the drivers and Linux network stack.

- Good experience with Linux, Command Line Tools and Bash scripting
- Programming skills in C and Python (and VHDL)
- Knowledge of Internet Networking Technologies, in particular OSI layer protocols

In order to research on energy-efficient and
low-latency network nodes for next-generation
networks, we are setting up a hardware testbed
with FPGA-based Network Interface Accelerator
Cards in the form of Xilinx Alveo FPGA boards.
Previous research in the area of Network Interface
Cards (NICs) at our chair led to HDL Designs of
Packet Processing Pipelines on older generation
FPGAs, which shall serve as basis for further
research on Xilinx Alveo FPGA boards.

Therefore, the goal of this work is to port these existing HDL Designs to the new FPGAs. This includes analyzing the existing designs, extracting the required logic and integrating it into the OpenNIC framework. Further, the functionality of the designs has to be verified by testing.

- Experience with Linux, Command Line Tools and Bash scripting
- Programming skills in VHDL/Verilog and C (and Python)
- Experience with FPGA Design and Implementation