6G-life

With research beginning on the next generation of mobile communications 6G, TUM joins forces with TU Dresden in the BMBF funded project 6G-life to develop new approaches regarding sustainability, security, resilience and latency in mobile communications.

Hereby, LIS is engaged in exploring new architectures and architecture extensions for network interface cards (NICs) in processing nodes. This is part of the chairs endeavor to investigate how much intelligence can be brought to the network interface, taking into account the specific needs of certain networking domains and applications.

Research Focus

Many 6G applications, such as extended reality (XR) or autonomous driving, will require low latency control loops to be closed over the network, thereby requiring processing near the user and decision-making early in the data path. This leads to a large increase in Edge Computing and a growing amount of differently dimensioned, heterogenous processing nodes. Since changing user and application behaviour can exert very volatile traffic characteristics and processing requirements, such processing nodes have to interact with the network adaptively and energy-efficiently, also to avoid overprovisioning single nodes.

Therefore, we at LIS want to explore how to extract information on current traffic characteristics and processing requirements in the NIC and how to use this information to efficiently provision the servers processing resources and reflexively react to changing conditions. More concretely, this involves:

  • designing a packet processing architecture with the required logic to extract information from incoming traffic
  • performing power management of the host CPU and its heterogenous resources
  • making processing decisions early in the data path, reducing the load on the CPU

and much more. We are prototyping these contributions on FPGA-based NICs in a multi-server testbed at our chair.

6G Testbed

The LIS 6G Testbed and Demonstrator consists of 2 AMD Epyc Server nodes and 4 AMD Ryzen PC nodes, which are equipped with several Xilinx FPGAs (NetFPGA SUME and Alveo), as well as commercial Intel NICs. They are used for prototyping 6G-specific SmartNIC extensions, providing proof-of-concept evaluation and demonstration in a physical networking testbed. The nodes can be used in a variety of ways, depending on the specific use case and evaluation setup. The figure on the right shows an exemplary representation of the nodes in a typical 6G use case.

Involved Researchers

Marco Liess

Klajd Zyla

Franz Biersack

Student Work

Offered Topics

Are you interested in contributing to 6G-life? If you don't find an interesting topic listed here, sometimes there is also the possibility to define a topic matching your specific interests. If you have questions about the 6G-life project and student works at our chair, please contact Marco Liess.

Ongoing

FPGA-based Network Tester for 100 Gbps

Beschreibung

With the advent of research on the next generation of
mobile communications 6G, we are engaged in exploring
architecture extensions for Smart Network Interface Cards
(SmartNICs). To enable adaptive, energy-efficient and
low-latency network interfaces, we are prototyping a
custom packet processing pipeline on FPGA-based NICs,
partially based on the open-nic project
(https://github.com/Xilinx/open-nic).

To test the performance of a SmartNIC-assisted server
under peak loads and achieve precise measurements of
key performance indicators (KPIs) such as throughput and latency, an FPGA-based Network Tester for 100 Gbps links shall be implemented and tested. For this, the Alveo U55C FPGA-based SmartNICs shall be used. With packet generation and throughput and latency measurements in hardware, maximum performance and precision should be reached.

The goal of this work is to implement the required logic modules in HDL (Verilog), integrate these modules into the OpenNIC Shell platform and test the design on the Alveo U55C FPGAs. Additionally, a software-interface to control the network tester can be developed, building up on a previous 10 Gbps Network Tester design. The design should also be evaluated regarding the performance of the packet generation as well as the precision in throughput and latency measurement.

Voraussetzungen

  • Programming skills VHDL/Verilog and C (and Python)
  • Good Knowledge of computer networks, OSI layer model and protocols
  • Comfortable with the Linux command line and bash
  • Preferably practical experience in FPGA design and implementation

Betreuer:

Marco Liess

Hardware Interrupt Generation for Smart Servers

Beschreibung

With the advent of research on the next generation of
mobile communications 6G, we are engaged in exploring
architecture extensions for Smart Network Interface Cards
(SmartNICs). To enable adaptive, energy-efficient and
low-latency network interfaces, we are prototyping a
custom packet processing pipeline on FPGA-based NICs,
partially based on the open-nic project
(https://github.com/Xilinx/open-nic).

To improve the performance and energy efficiency of a
modern server, SmartNICs can be used to preprocess
incoming packets and gather characteristics on traffic and processing requirements. This information can be used to change the processing behavior of the server and react to the dynamic network and processing requirements. To do so, the server has to be notified of detected events using an interrupt.

The goal of this work is to implement hardware-based interrupt generation in an FPGA-based SmartNIC using HDL and PCIe IP cores, registering the interrupt with the Linux interrupt driver as well as writing a suitable ISR (interrupt service routine). This mechanism should be functionally verified in a hardware testbed and evaluated regarding the latency of the interrupt. Additionally, the work could be extended to include setting the core affinity of an interrupt and generating interrupts destined for specific CPU cores.

Voraussetzungen

  • Programming skills in VHDL/Verilog and C (and Python)
  • Practical experience with FPGA Design and Implementation
  • Good Knowledge of computer architecture and low-level software / drivers
  • Comfortable with the Linux command line and bash

Kontakt

Marco Liess, M. Sc.

Tel.: +49.89.289.23873
Raum:
N2139
Email:
marco.liess@tum.de

Betreuer:

Marco Liess

Webserver Setup for Benchmarking of a SmartNIC-assisted Server

Beschreibung

With the advent of research on the next generation of
mobile communications 6G, we are engaged in exploring
architecture extensions for Smart Network Interface Cards
(SmartNICs). To enable adaptive, energy-efficient and
low-latency network interfaces, we are prototyping a
custom packet processing pipeline on FPGA-based NICs,
partially based on the open-nic project
(https://github.com/Xilinx/open-nic).

To properly evaluate the performance of a
SmartNIC-assisted server, a webserver-based application
shall be setup in a Linux OS environment and tested with different request rates. Additionally, the performance of single- vs. multicore platforms for one and multiple webserver instances should be compared. CPU core isolation mechanisms can be used to setup such scenarios on the server.

The goal of this work is to setup a webserver (e.g. NGINX), potentially with a database backend (e.g. MongoDB) and develop a measurement and testing methodology for performance benchmarking of a SmartNIC-assisted server. This includes throughput and latency measurements, as well as analysis of the CPU and network utilization.

Voraussetzungen

  •     Programming skills C and Python
  •     Good Knowledge of computer networks, OSI layer model and protocols
  •     Comfortable with the Linux command line and bash
  •     Preferably experience with Linux drivers and low-level software

Kontakt

Marco Liess, M. Sc.

Tel.: +49.89.289.23873
Raum:
N2139
Email:
marco.liess@tum.de

Betreuer:

Marco Liess

Implementation and Evaulation of Hardware Match-Action Tables on FPGA

Beschreibung

With the advent of research on the next generation of
mobile communications 6G, we are engaged in exploring
architecture extensions for Smart Network Interface Cards
(SmartNICs). To enable adaptive, energy-efficient and
low-latency network interfaces, we are prototyping a
custom packet processing pipeline on FPGA-based NICs,
partially based on the open-nic project
(https://github.com/Xilinx/open-nic).

Incoming packet flows should be differentiated and differently
processed, which is typically solved with match-action tables (MATs).
MATs match on a certain packet condition (e.g. packet header 5-tuple) and execute an according action (e.g. dropping, forwarding or modifying the packet). A recent Xilinx IP core implements MATs that can be programmed with P4, a programmable packet processing language gaining momentum in networking. The goal of this work is to investigate the implementation of MATs in hardware, integrate them into our current HDL design based on open-nic and test and evaluate the results.

Voraussetzungen

  •     Programming skills in VHDL/Verilog and C (and Python)
  •     Practical experience with FPGA Design and Implementation
  •     Good Knowledge of computer networks, OSI layer model and protocols
  •     Preferably basic knowledge of P4 packet processing language

Kontakt

Marco Liess, M. Sc.

Tel.: +49.89.289.23873
Raum:
N2139
Email:
marco.liess@tum.de

Betreuer:

Marco Liess
Completed

Kontakt

Marco Liess, M.Sc.

Tel.: +49.89.289.23873
Raum: N2139
Email: marco.liess@tum.de

 

Betreuer:

Marco Liess

Kontakt

Marco Liess, M.Sc.

Tel.: +49.89.289.23873
Raum: N2139
Email: marco.liess@tum.de

Betreuer:

Marco Liess

Kontakt

Marco Liess, M.Sc.

Tel.: +49.89.289.23873
Raum: N2139
Email: marco.liess@tum.de

 

Betreuer:

Marco Liess

Kontakt

Marco Liess, M.Sc.

Tel.: +49.89.289.23873
Gebäude: N1 (Theresienstr. 90)
Raum: N2139
Email: marco.liess@tum.de

 

Betreuer:

Marco Liess

Kontakt

Marco Liess, M.Sc.

Technische Universität München
Lehrstuhl für Integrierte Systeme
Arcisstr. 21, 80333 München

Tel.: +49.89.289.23873
Raum: N2139
Email: marco.liess@tum.de

 

Betreuer:

Marco Liess

Publications

  • Marco Liess, Julian Demicoli, Tobias Tiedje, Matthias Lohrmann, Matthias Nickel, Marco Luniak, Dimitris Prousalis, Thomas Wild, Ronald Tetzlaff, Diana Göhringer, Christian Mayr, Karlheinz Bock, Sebastian Steinhorst, Andreas Herkersdorf: X-MAPE: Extending 6G-connected Self-adaptive Systems with Reflexive Actions. 2023 IEEE Conference on Network Function Virtualization and Software Defined Networks (NFV-SDN), 2023 mehr… BibTeX