Switches and network interface cards receive traffic at hundreds of Gbit/s and process packets with stringent latency requirements. The bandwidth and forwarding latency of the interconnect highly affects the performance of the whole design. The goal of this seminar work is to investigate and compare state-of-the-art interconnects in terms of metrics such as throughput, latency, priority-awareness, scalability and chip area.

[1] Kurth, Andreas, et al. "An open-source platform for high-performance non-coherent on-chip communication." IEEE Transactions on Computers 71.8 (2021): 1794-1809.

[2] Lin, Jiaxin, et al. "PANIC: A high-performance programmable NIC for multi-tenant networks." Proceedings of the 14th USENIX Conference on Operating Systems Design and Implementation. 2020.

DRAM modules are indispensable for modern computer architectures. Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density.

However, DRAM accesses are rather slow and require a dedicated DRAM controller that coordinates the read and write accesses to the DRAM as well as the refresh cycles.

In order to reduce the DRAM access latency, DRAM controllers provide sophisticated mechanisms, such as access predictors or built-in caches. The goal of this Seminar is to study and compare DRAM controller designs with several optimizations and present their benefits and usecases. A starting point of literature will be provided.

B.Sc. in Electrical engineering or similar degree

Cache Design have by design some compulsory cache misses, i.e. the first access of a certain cacheline will typically result in a cache miss, since the data is not present in the cache hierarchy yet.

In order to reduce this, caches can be extended by prefetching mechanisms that speculatively prefetch some cachelines before they first get accessed.

The goal of this Seminar is to study and compare different cache prefetcher designs and present their benefits and usecases. A starting point of literature will be provided.

B.Sc. in Electrical engineering or similar degree

This seminar should explore innovations in optical interconnects using silicon photonics.

DRAM modules are indispensable for modern computer architectures. Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density.

However, DRAM accesses are rather slow and require a dedicated DRAM controller that coordinates the read and write accesses to the DRAM as well as the refresh cycles.

In order to reduce the DRAM access latency,memory prefetching is a common technique to access data prior to their actual usage. However, this requires sophisticated prediction algorithms in order to prefetch the right data at the right time.

The goal of this Seminar is to study and compare several memory prefetching algorithms and present their benefits and usecases. A starting point of literature will be provided.

B.Sc. in Electrical engineering or similar degree

Due to the rising number of sensors and actuators in modern cars, aimed at enabling features like autonomous dring or car-to-car communication, the on-board electrical/electronic (E/E) architecture is transitioning from the established domain-based design to the new zonal structure. There, each zone is assigned a high-performance zone module tasked with processing the data of all devices within its area. To develop next-generation SoCs and load balancer designs for efficiently distributing and processing the whole spectrum of accumulated workloads, a precise understanding of the sensors and actuators present on the automotive network, as well as the resulting compute tasks and their associated workload is required.

The goal of this seminar topic hence is to compile an overview of processing tasks for upcoming zonal compute nodes, along with a rough expectation of their occurence and required number of instructions.

Cache Design have by design some compulsory cache misses, i.e. the first access of a certain cacheline will typically result in a cache miss, since the data is not present in the cache hierarchy yet.

In order to reduce this, caches can be extended by prefetching mechanisms that speculatively prefetch some cachelines before they first get accessed.

The goal of this Seminar is to study and compare different cache prefetcher designs and present their benefits and usecases. A starting point of literature will be provided.

B.Sc. in Electrical engineering or similar degree

DRAM modules are indispensable for modern computer architectures. Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density.

However, DRAM accesses are rather slow and require a dedicated DRAM controller that coordinates the read and write accesses to the DRAM as well as the refresh cycles.

In order to reduce the DRAM access latency, DRAM systems are often combined with prefetching mechanisms. The goal of this Seminar is to study and compare Prefetching mechanism for DRAM systems and present their benefits and usecases. A starting point of literature will be provided.

B.Sc. in Electrical engineering or similar degree

DRAM modules are indispensable for modern computer architectures. Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density.

However, DRAM accesses are rather slow and require a dedicated DRAM controller that coordinates the read and write accesses to the DRAM as well as the refresh cycles.

In order to reduce the DRAM access latency, DRAM controllers provide sophisticated mechanisms, such as access predictors or built-in caches. The goal of this Seminar is to study and compare DRAM controller designs with built-in caches and present their benefits and usecases. A starting point of literature will be provided.

B.Sc. in Electrical engineering or similar degree

Multi-Core Processors find their way into more and more application domains and allow for the parallel execution of multiple tasks which are independent from each other. Especially in areas like vehicle networks or wearable computing, not only processing performance, but also energy efficiency is of high importance. To save power during periods of low processing demand, Dynamic Voltage and Frequency Scaling (DVFS) is a mechanism to adaptively scale the clock frequency and supply voltage. Modern CPUs even allow for individual frequency and voltage configurations per CPU core. And while the discrete voltage and clock levels might be set by the used CPU design, the algorithm deciding on when to increase or decrease these metrics can sometimes be freely customized by the user.

The goal of this seminar topic is to investigae state of the art approaches for high efficiency DVFS scaling algorithms.

In this seminar work, the memory capacity of echo state networks shall be analyzed by reviewing relevant literature. The following questions indicate possible topics for discussion and analysis:

• How can memory in echo state networks be characterized and differentiated?
• How can the memory capacity be measured?
• Which parameters and / or architectural design decisions have an effect on the memory capacity?

The following papers may be used as a starting point:

1. Jaeger: "Short term memory in echo state networks"
2. Verstraeten et al.: "Memory versus Non-Linearity in Reservoirs"
3. Rodan and Tino: "Minimum complexity echo state network"

To successfully carry out this seminar work, you should:

• work independently and self-organized
• have strong reading and writing comprehension of scientific papers
• perform structured literature research

LCS, especially XCS, have been shown to be effective for design space exploration.

Recently they have been applied to control problems more often.

Hereby, it's important to consider if the learning is applied online / while execution or offline / before execution.

This seminar should investigate the challenges of employing RL to Real-Time Problems.

- save exploration
- inserting new rules

When we talk about "caches" is's clear, that we talk about dedicated hardware.

But there exist many other types of caching in the context of IT. Just have a look at the search results here: https://scholar.google.de/scholar?q=caching

This seminar should investigate in which contexts computer scientists talk about caching, which purpose it has and what are the HW and SW requirements.

RL is able to play games like Go (https://www.nature.com/articles/nature16961).

But how does it suceed in control?

This seminar should look into how RL engineers are trying to solve control problems: https://arxiv.org/pdf/1806.09460.pdf

Switches and network interface cards receive traffic at hundreds of Gbit/s and process packets with stringent latency requirements. The bandwidth and forwarding latency of the interconnect highly affects the performance of the whole design. The goal of this seminar work is to investigate and compare state-of-the-art interconnects in terms of metrics such as throughput, latency, priority-awareness, scalability and chip area.

[1] Kurth, Andreas, et al. "An open-source platform for high-performance non-coherent on-chip communication." IEEE Transactions on Computers 71.8 (2021): 1794-1809.

[2] Lin, Jiaxin, et al. "PANIC: A high-performance programmable NIC for multi-tenant networks." Proceedings of the 14th USENIX Conference on Operating Systems Design and Implementation. 2020.

The incoming traffic load and with it the computing requirements on network processing nodes such as edge servers can span multiple magnitudes in a matter of milliseconds and less. The systems are ususally dimensioned to cope with peak loads, resulting in a low resource utilization when traffic is little. To ensure a highly energy-efficient resource utilization, dynamic power management with respect to fluctuating processing requirements is necessary to reduce the power consumption (e.g. by dynamic voltage frequency scaling (DVFS) or power gating) in times of low traffic load.

The goal of this seminar is to establish an overview on current approaches for power management in network processing nodes such as edge servers. Hereby, the focus lies on the employed methods, the timescales with which they operate and their impact on processing performance indicators such as throughput and latency.

A starting point for the literature research can be:
https://dl.acm.org/doi/pdf/10.1145/3466752.3480098

Explore DQN, double-DQN, imitation learning, LCTs and Q-table based learning agents for scheduling, power, energy and temperature management in multi/many core heterogenous processors.