Description
Neural networks (NNs) have seen great improvements over the last decades and have consequently been adopted for a multitude of applications. While much more capable in certain areas than prior solutions, NNs have one big drawback.

A neural network requires much more power than traditional computational models, making them generally unsuited for embedded devices. The rapid adoption also poses challenges for high performance models, as the amount of processing power required for widespread use strains the existing power grid - with construction of AI data-centers significantly outpacing construction of new power plants. Clearly this growth is unsustainable unless these challenges are addressed.

In part to address these issues, research has been ongoing into techniques which may avoid the high computational cost and power dissipation of standard neural networks, such as Convolutional Neural Networks (CNNs). Particularly for event driven computation, models such as Spiking Neural Networks (SNNs) and/or asynchronous neural networks offer potentially significant benefits; as event driven applications only require that computation is performed once a new event occurs, power can be saved by only being active when a computation is required. Asynchronous circuits take this idea to the extreme by completely avoiding all dynamic power dissipation except when subcircuits have valid inputs available.

Task
For this seminar topic, the student is expected to look into the state-of-the-art for asynchronous neural networks and provide a summary of relevant research. Papers that could serve as potential starting points can be seen below, but the student is free to pursue the topic as they want, within the confines of the scope given in this description. 

Starting points

• A 28nm Configurable Asynchronous SNN Accelerator with Energy-Efficient Learning
• DYNAP-SE2: a scalable multi-core dynamic neuromorphic
  asynchronous spiking neural network processor
• Design and Tool Flow of a Reconfigurable Asynchronous
  Neural Network Accelerator
• A 2048-Neuron Spiking Neural Network
  Accelerator with Neuro-Inspired Pruning and
  Asynchronous Network on Chip in 40nm CMOS

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Voraussetzungen

Prefetching is a widely used technique in modern processors to mitigate the memory wall problem by fetching data into faster memory levels before it is actually needed. While prefetching has been extensively studied and deployed in CPUs, where hierarchical cache designs (L1, L2, and off-chip DRAM) dominate, GPUs present a very different challenge.

GPUs are now central to diverse applications ranging from artificial intelligence to scientific computing. Their massively parallel architecture and SIMT execution model create distinct memory access behaviors compared to CPUs. Consequently, conventional CPU prefetching mechanisms are often ineffective or even harmful when applied to GPUs. This has led to the development of GPU-specific prefetching strategies that account for the unique architectural features and execution patterns of GPUs.

The goal of this seminar is to study and compare different GPU prefetching mechanisms. By reviewing recent research papers, participants will gain an understanding of how these mechanisms work, their advantages and limitations, and under what conditions they can improve GPU performance.

Voraussetzungen