Masterarbeiten

About the Project
Modern in-vehicle networks (IVNs) increasingly rely on Automotive Ethernet as the communication backbone, with SOME/IP serving as the dominant service-oriented protocol for inter-ECU communication. As IVN complexity grows, communication anomalies—arising from software faults, timing failures, or unexpected traffic behaviors—pose challenges to functional safety. Within the EMDRIVE project, our team is developing a Diagnosis Unit (DU) on the Xilinx ZCU102 platform that monitors Automotive Ethernet traffic in real time. The current PL-side implementation relies on static rule-based packet checks, which limits its detection capability against evolving and unseen behaviors.

Project Description
The goal of this thesis is to design, implement, and evaluate a machine learning-based anomaly detection module on the Programmable Logic (PL) side of the ZCU102, capable of processing SOME/IP traffic at line rate without dropping packets. The module learns the normal behavior of the network at the flow and header level and flags deviations as anomalies, providing higher detection accuracy and adaptability than the existing rule-based unit. Deep payload semantics are out of scope. The work targets 100BASE-T1, with timing-based scalability analysis toward 1000BASE-T1. The thesis focuses on static-model deployment, where on-line adaptation to behavioral shift is identified as a relevant follow-on direction. 

Phase 1 - Foundational (must complete):

• Literature study and method selection: Review existing ML-based anomaly detection methods for Automotive Ethernet and select one functionally proven approach (e.g., quantized MLP, autoencoder, or isolation forest) suitable for FPGA deployment.
• Anomaly taxonomy: Define a behavioral anomaly taxonomy for SOME/IP traffic covering topological, temporal, volumetric, structural, and semantic deviation classes at flow and header level.
• Software baseline and reference behavior: Implement and validate the selected method in Python on a publicly available Automotive Ethernet dataset. Document the rule set of the existing PL-side detector to establish a meaningful comparison baseline.
• Quantization and hardware generation: Apply quantization-aware training and generate a synthesizable inference IP using FINN or hls4ml, verify functional correctness in simulation.

Phase 2 - Core (target):

• PL integration: Integrate the inference IP with the existing Ethernet parser via AXI4-Stream, implement SOME/IP header parsing and feature extraction in hardware, expose anomaly score and class to the PS via AXI-Lite registers.
• On-board evaluation: Measure detection accuracy, false-positive rate, latency, throughput, and resource utilization on the ZCU102 at 100BASE-T1. 

Key Responsibilities: 

• Survey relevant literature and select a single proven detection method as the foundation.
• Train, validate, and quantize the model in Python.
• Generate, integrate, and verify the FPGA inference IP on the ZCU102.
• Evaluate the system end-to-end and document results clearly.
• Present intermediate progress in periodic meetings

Voraussetzungen

As automotive architectures transition from legacy bus systems to high-speed Automotive Ethernet, the Audio Video Transport Protocol (AVTP) has become the standard for transporting time-sensitive data, including ADAS camera feeds, infotainment streams, and critical control traffic. However, this transition opens new attack vectors: malicious frames can be injected to freeze the camera or spoof control messages within the AVTP stream, potentially leading to catastrophic failures.

The current detection methods exploit the consistency of the Ethernet Frame header. They can detect malicious packets with abnormal sequence numbers in their headers. However, if the anomalies happen before the Ethernet transaction (on the broadcaster or in the real world) or the intrusion is well designed to have a normal header, the current detection systems are at a loss.

To address this scenario, we want to develop an unsupervised Anomaly Detection System to detect abnormal behavior in AVTP packets. More specifically, we want to detect deviations across several consecutive image frames to assess the normality of each image at the packet level. The idea is that the Ethernet packets are supposed to contain the data in the same manner. For example, the first packet should always contain the first chunk of the Intra Frames, and the number of packets represents how different the two consecutive Predictive Frames are. So the image to compare the content is equivalent to comparing a small part of the image.

Our research targets three different circumstances:

• An anomaly in the real world, e.g., a damaged camera or obstacles in front of the camera.
• Intrusion on the broadcast, memory replacement, leading to a sequence of AVTP frames with normal headers.

• Injection during transmission. The malicious attacker sends replayed frames with abnormal headers.

Since the AVTP protocol is commonly used to transmit video footage, we can transfer the concept of Abrupt Detection of Image into our system.

The work can be separated into the following parts.

• Literature review for image cut detection (feature extraction)
• Implement a lightweight, unsupervised anomaly detection system for the image sequence.
• Transfer it to the AVTP Ethernet Frames
• If possible, expand the model to the general Ethernet protocols.

Voraussetzungen

Overview

Packet-based FEC enables lower latency over packet erasure channels by reducing retransmissions. This is performed by generating repair symbols, which are linear combinations of a set of source packets, and transmitting them along with the original source packets. As long as enough packets are received, any lost or dropped packet may be recovered by the receiver. A challenge of performing FEC in hardware is handling the buffering of packets. 

The objective of this thesis is to implement a packet buffer for packet-based FEC on an FPGA-based SmartNIC. Once implemented, the packet buffer should be tested and evaluated under different, realistic traffic scenarios. 

Challenges and Objectives 

Packets have to be stored until the repair packets can be generated. When the required number of packets (one block) have been buffered, they are fed to the FEC encoder. The packets must furthermore be output in the sequence of arrival, and therefore this sequence must also be stored. Once the packets have been processed, the buffer space can be freed again. 

FEC encoding must be done on a per-flow basis, which makes memory management challenging. Firstly, as packets of different flows may arrive in an interleaved manner, packets belonging to different flows must be managed via per-flow virtual buffers. This has the consequence that packets belonging to the same flows will often not reside in continuous blocks of memory, which leads to memory fragmentation. Secondly, the length of packets is variable (64B to 1500B) and is not known in advance, so it must be handled on-the-fly. To address these issues and to make efficient use of available memory, an intelligent management scheme should therefore be implemented.  

Another point is that, as the FEC is transparent to the application layer, the buffer must be preconfigured to support the desired number of flows and their FEC configuration. The number of flows should be a design time configuration whereas the FEC configuration (block size, redundancy factor, etc.) should be configurable at runtime.  

Finally, if time permits, the buffer should be expanded to also serve the RX path, by buffering packets received by the network before they can be decoded by the FEC decoder.

To improve the performance and energy efficiency of a
modern server, SmartNICs can be used to preprocess
incoming packets and gather characteristics on traffic
and processing requirements, as well as offer the possibility
to offload and accelerate specific functionalities. In the
context of Data Distribution in Vehicular Networks for
Automated Driving, an existing protocol and software
solution [1] offers the potential for SmartNIC-acceleration.
This state-of-the-art solution relies on selective data
distribution in a ROS2-environment to reduce the amount of
data transferred and thereby improve latency and efficiency.
While the offered software implementation already shows significant improvements, offloading certain protocol and packet processing to the SmartNIC promises much greater gains by avoiding expensive software loops and enabling hardware-accelerated processing. 

The goal of this work is to implement the network protocol developed in [1] in FPGA-hardware, preferably using the P4 framework [2]. An existing implementation of the AMD Vitis Net P4 IP core can be used as a starting point. Further, the image processing can be offloaded to the SmartNIC and accelerated using parallel hardware and the onboard HBM on the SmartNIC's FPGA. This requires a custom RTL implementation of image format transformation and caching logic. The existing software implementation shall be used as a design reference and comparison in terms of performance evaluation.

[1] N. Sperling and R. Ernst, "Reducing Communication Cost and Latency in Autonomous Vehicles with Subscriber-centric Selective Data Distribution," 2024 IEEE 99th Vehicular Technology Conference (VTC2024-Spring), Singapore, Singapore, 2024, pp. 1-7

Voraussetzungen

Hardware preloading mechanisms, as investigated in the current project, must balance latency hiding against bandwidth efficiency. While page-based preloading can effectively amortize memory access latency, it may also lead to unnecessary bandwidth consumption when memory access patterns change dynamically. This thesis builds upon an existing page-based preload unit that incrementally transfers memory pages. The current baseline design employs fixed policies for page switching and preload completion, independent of the observed usefulness of partially loaded pages.

The objective of this work is to enhance the preload unit with self-adaptive control mechanisms that dynamically adjust preloading behavior based on runtime feedback. In particular, the preload unit shall monitor the usefulness of partially preloaded pages, enabling early termination of preload operations when further progress is unlikely to produce additional cache hits. Furthermore, the student will extend the page switching logic to consider multiple factors, including page priority, observed reuse, preload progress, and interruption frequency.

Experimental observations indicate that pages suspended due to page switching are often not accessed again in the future, raising the question under which conditions such pages should remain in the priority queue for continued preloading. In addition, the thesis will investigate more advanced priority strategies that augment the existing temporal and spatial locality scheme with runtime feedback and observed memory behavior.

All proposed strategies shall be developed and evaluated using RTL-based simulation as well as FPGA-based implementations. The overall goal of this thesis is to derive a self-adaptive and enhanced version of the existing preload unit. The enhanced design will be evaluated using synthetic microbenchmarks and representative benchmarks. The evaluation will quantify improvements in bandwidth efficiency and preload effectiveness under varying memory access characteristics.

Voraussetzungen