Masterarbeiten

Since DRAM typically come with much higher access latencies than SRAM, many approaches to reduce DRAM latencies have already been explored, such as Caching, Access predictors, Row-buffers etc.

In the CeCaS research project, we plan to employ an additional mechanism, in detail a preloading mechanism of a certain fraction of the DRAM content to a small on-chip SRAM buffer. Thus, it is required to predict potentially next-accessed Cachelines, preload them to the SRAM and answer subsequent memory requests of this data from the SRAM instead forwarding them to the DRAM itself.

This functionality should be implemented as a TLM/SystemC model using Synopsys Platform Architect. A baseline system will bw provided, the goal is to implement this functionality in its simplest form as a baseline. Depending on the progress, this can be extended or refined in subsequent steps.

A close supervision, especially during the inital phase, will be guaranteed. Nevertheless, some experience with TLM modelling (e.g. SystemC Lab of LIS) or C++ programming is required.

• Experience with TLM modelling (e.g. SystemC Lab of LIS)
• B.Sc. in Electrical Engineering or similar

At LIS, we want to use the Duckietown hardware and software ecosystem for experimenting with our reinforcement learning based learning classifier tables (LCTs) as part of the control system of the Duckiebots: https://www.ce.cit.tum.de/lis/forschung/aktuelle-projekte/duckietown-lab/

More information on Duckietown can be found on https://www.duckietown.org/.

Currently, we are developing the infrastructure for our LCT experiments.
While several students are improving on the autonomous driving abilities of the Duckiebots, this work's goal is to develop a system which provides insights into the bots' driving performance.
Therefore, we need objective measurements by a third party which allow us to compare the driving performance (average speed, deviation from optimal line, …) between bots which might run different SW.
To compare specific scenarios, these measurements shouldn't only be a time series, but be enhanced by the position of the respective bot at this point in time. Similar to the modern sports apps: https://www.outdooractive.com/de/route/wanderung/tegernsee-schliersee/auf-dem-prinzenweg-vom-schliersee-an-den-tegernsee/1374189/#dm=1.

Towards this goal it's required to develop a camera-based mechanism, which identifies bots in the field, extracts their concrete position and calculates certain metrics like direction, velocity, on / off lane, spinning, deviation from ideal line, ….
This data then should be logged to be analyzed + visualized later.

Depending on the type of work (BA/FP vs MA) this work might include to enhance these measurements with internal data of the bots to compare internal and external perception, and to develop tools for easy analysis.

• independent work style
• problem solving skills
• computer vision knowledge (openCV)
• programming skills (we are open which framework is used - Python, C++ (Qt), Matlab, ...
• Linux basics (permissions)

The Chair of Integrated Systems participates in the DFG Priority Program “Resilient Connected Worlds” by the German Research Foundation (SPP 2378). Our goal is to investigate which resilience functions, that conventionally are provisioned by the central compute resources of Internet Networking or Compute Nodes, can meaningfully be migrated onto the Network Interface Card (NIC). By inspecting packet streams at full line rate (10 – 40 Gbps) a set of resilience functions, such as access shields against a known set of traffic flows or redundant flow processing for a selected and configured number of flows, shall be offloaded from centralized compute resources and offered in a more performant and energy-efficient manner. Flows are identified by their so-called 5-tuple consisting of source-/destination IP addresses and transport protocol ports as well as the protocol field of the IP packet header.
 
During the Bachelor/Master Thesis, you will develop VHDL code for realizing one or more of the SmartNIC Resilience building blocks: 5 tuple address matching against a preconfigured set of addresses, perform the packet duplication for delivery to different processor cores or threads, investigate methods to flexibly perform the address match on the entire or a variable subsection of the 5 tuple array.

• VHDL coding, synthesis and FPGA prototyping
• Braodband communication or Internet Networking Technologies,
  in particular OSI Layer packet header formats
• Digital circuit design

Reinforcement learning (RL) has been widely used for run-time management on multi-core processors. RL-based controllers can adapt to varying emerging workloads, system goals, constraints and environment changes by learning from their experiences.

Neural Networks are a set of ML methods which are inspired by the human brain, mimicking the way that biological neurons signal to one another.

In this work, you will

1. Understand the working of Neural Networks. Implement a neural network in C.

2. Understand the architecture of the Leon3 based SoC.

3. Use neural networks to learn and control the processor voltage and frequency in runtime to optimize performance and power.

4. Design, test and implement the work on Xilinx FPGA

To successfully complete this project, you should already have the following skills and experiences: 
• Good VHDL and C programming skills 
• Good understanding of MPSoCs
• Self-motivated and structured work style
• Knowledge of machine learning algorithms

CONTEXT:

Future cars have a wide variety of sensors such as cameras, LiDARs and RADARs that generate a large amount of data. This data has to be sent via an intra-vehicular network (IVN) to further processing nodes and, ultimately, actuators have to react to the sensor input. Inbetween the processing steps the intra-vehicular network has to ensure that all of the data and control signals reach their destination in time. Hence, next to a large amount of data, there are also strict timing constraints that the intra-vehicular network has to cope with. Therefore, the so called time-sensitive networking (TSN) has been introduced. The functional safety of such networks plays an important role against the background of higly automated driving. Emerging errors have to be detected early and potential countermeasures have to be taken to keep the vehicle in a safe state. Therefore, highly sophisticated monitoring and diagnosis algorithms are a key requirement for future cars. (See Project EMDRIVE)

THIS WORK:

Based on an existing IVN simulation Ethernet traffic can be generated and, subsequently, investigated for anomalous behavior. The challenge is to detect and classify anomalous behavior without any preknowledge on timing and nature of the same. Therefore, several methods can be applied, ranging from static measurement methods to AI based anomaly detection. The focus of this work could lie on the application of LSTM or transformer-based models. The preferred development environment builds on python and related libraries like TensorFlow and Keras. Comparing at least two different anomaly detection methods and exploring, as well as discussing their respective advantages rounds up the master thesis. (M)

If you are interested, feel free to contact me! Please send your CV as well as a recent transcript.

In the course of the master's thesis it is possible to take some time to work into the related technichal fields. However, it is advisable to already bring some understanding of the following fields:

OSI-Layer,
Basics in automotive E/E architectures,
Basics in simulations (OMNET++)
Basics in C++ and Python required
First experience with AI (TensorFlow and Keras) desired

CONTEXT:

Future cars have a wide variety of sensors such as cameras, LiDARs and RADARs that generate a large amount of data. This data has to be sent via an intra-vehicular network (IVN) to further processing nodes and, ultimately, actuators have to react to the sensor input. Inbetween the processing steps the intra-vehicular network has to ensure that all of the data and control signals reach their destination in time. Hence, next to a large amount of data, there are also strict timing constraints that the intra-vehicular network has to cope with. Therefore, the so called time-sensitive networking (TSN) has been introduced. The functional safety of such networks plays an important role against the background of higly automated driving. Emerging errors have to be detected early and potential countermeasures have to be taken to keep the vehicle in a safe state. Therefore, highly sophisticated monitoring and diagnosis algorithms are a key requirement for future cars. (See Project EMDRIVE)

Our approach for such diagnosis builds on non-intrusively monitoring the intra-vehicular network by snooping on data traffic at an interconnect in the car. An analysis of the traffic shall give information about anomalies that occur inside the network as symptoms of an error inside the electrical architecture.

FORSCHUNGSPRAXIS:

Substance of this work is to first work into an existing simulation environment for an IVN with TSN in OMNET++. Based on the already existing work, several extensions have to be implemented (C++ based) in the simulation environment to mimic certain fault classes like delayed messages, broken links, etc. These fault classes can then later on be injected into the IVN simulation. (FP or IDP)

MASTERARBEIT:

Subsequently, the IVN simulation can be used to generate a stream of Ethernet traffic that can be investigated for aforementioned anomalous behavior. The challenge is to detect and classify anomalous behavior without any preknowledge on timing and nature of the same. Therefore, several methods can be applied, ranging from static measurement methods to AI based anomaly detection. The focus of this work could lie on the application of LSTM or transformer-based models. The preferred development environment builds on python and related libraries like TensorFlow and Keras. Comparing at least two different anomaly detection methods and exploring, as well as discussing their respective advantages rounds up the master thesis. (M)

It is desired to combine Forschungspraxis and Master thesis in the context of this project. In this way, the time during Forschungspraxis can be used to familiarize with the OMNET++ simulation environment.

If you are interested, feel free to contact me! Please send your CV as well as a recent transcript.

In the course of both projects (FP+MA) it is possible to take enough time to work into the related technichal fields. The main skills that will be developed and needed during this project are the following:

OSI-Layer,
Basics in automotive E/E architectures,
Basics in simulations (OMNET++)
Basics in C++ and Python
Experience with AI (TensorFlow and Keras)

Microchip PolarFire SoC is a Flash FPGA with a quad-core RISC-V processor. With this device, we are developing applications including motor drive, laser frequency adjustment or instrument control in general.

In thre frame of this master thesis, you are working with the ICICLE Kit, the PolarFire SoC evaluation board. It includes communication interfaces, external memories and embedded programmers

Depending on your experience and specific interest, you will be implementing functionalities using the design software Libero SoC, SmartHLS (FPGA design) or SoftConsole (SW design). Our applications usually include HW access, wherefore will have to build breadboards and take measurements in order to verify the functionality once implemented.

• Experience in FPGA/SoC design (VHDL, C/C++, SmartDesign, Vivado etc.) and system development (hardware, software and its connections)
• Knohow using laboratory instrumentation like oscilloscopes, spectrum analyzers and building test setups
• Problem solving skills and the potential to finding creative solutions