Masterarbeiten

Background: In modern embedded systems, microcontrollers are increasingly equipped with operating systems to manage complex tasks and optimize system performance. However, understanding the tasks being executed on these microcontrollers is crucial for system optimization, debugging, and security purposes. Traditional methods of task identification rely on invasive techniques, such as instrumentation or logging, which can alter the system's behavior and introduce overhead. 

 Objective: The primary goal of this master thesis is to design and develop a non-invasive method for detecting tasks executed on a microcontroller with an operating system, solely relying on the analysis of trace data. To achieve this, the student will leverage an existing tool called NITRO, written in Java, which has the capability to identify task executions on hard real-time systems. In this research, the student will utilize an AURIX microcontroller, running either AUTOSAR or FreeRTOS operating systems, assuming a single-core setup. 

Specifically, the student will focus on developing a new tool, written in C++, to analyze trace data generated by the microcontroller, with the aim of identifying the tasks being executed. Building upon the concepts and principles of the existing NITRO tool, the student will design and implement a novel approach to accommodate the AURIX microcontroller and the chosen operating systems. 

In the case of AUTOSAR, the student will take advantage of the standard's specification, which requires task switches to be written to a variable, thereby facilitating the identification of task executions. For FreeRTOS, the student will need to develop alternative methods to detect task switches. 

Once the tasks are successfully identified, the student will proceed to analyze the CPU usage of each task, as well as calculate the average, maximum, and minimum duration of each task. The outcome of this research is expected to provide a comprehensive understanding of task execution on microcontrollers with operating systems solely based on trace data analysis. 

The new tool, written in C++, should be capable of processing trace data from the AURIX microcontroller and providing detailed insights into task execution patterns, including CPU usage and task duration metrics. The tool should be designed with flexibility and scalability in mind, allowing for potential future extensions to accommodate other microcontrollers and operating systems. 

To clarify, some potential questions to consider are: 

• How can the concepts and principles of the existing NITRO tool be adapted and extended to accommodate the AURIX microcontroller and AUTOSAR/FreeRTOS operating systems in a C++ implementation?
• What specific trace data analysis techniques will be employed to identify task executions on the microcontroller, and how will these be implemented in the new C++ tool? 
• How will the student account for potential variations in task execution patterns between AUTOSAR and FreeRTOS operating systems, and how will these be addressed in the new tool? 
• What are the implications of this research for real-time system design and optimization, and how can the new tool be used to improve system performance and efficiency? 

Methodology: 

• Collect and preprocess trace data from a microcontroller with an operating system 
• Develop and implement algorithms for task identification using techniques such as machine learning or statistical analysis 
• Evaluate the performance of the proposed approach using metrics such as accuracy, precision, and recall 
• Investigate the impact of various factors, such as system load, task priority, and operative system version, on task identification 
• Obtain some statistical data on the CPU usage of each task and average duration. 

Expected Outcomes: 

• A novel approach for task identification on microcontrollers with hard real-time operating systems based on trace data analysis 
• A prototype implementation of the proposed approach using a suitable programming language and development environment 
• A comprehensive evaluation of the approach, including performance metrics and limitations 
• A written thesis document detailing the methodology, results, and conclusions

Requirements: 

• Bachelor in computer science, electrical engineering, or a related field 
• Experience with microcontrollers, operating systems, and embedded systems 
• Proficiency in one programming language such as C, C++, and Python 
• Familiarity with data analysis and machine learning techniques 
• Problem-solving skills and ability to work independently 

An upcoming trend in the development of computer architecture can be seen over the last few years. Next to the ever-increasing number of cores in one system, dedicated hardware accelerators for specific tasks are getting increasingly widespread. On the software side, multithreaded applications are gaining more popularity as one approach to maximize the utilization of the underlying hardware architectures. Here Intra-/Inter-Process Communication (IPC) becomes more and more of a limiting factor in these systems. Besides the data transfer, primarily used in Inter-Process Communication, the notification can be a time-consuming operation in IPC mechanisms.

The notification in an IPC is used to notify about some kind of event that occurred. In general, the event source can be either in software (user space or kernel space) or in hardware. However, in current systems, it is not possible to wait directly on events that occur in hardware with traditional notification mechanisms such as epoll but a helper software construct has to be used. For instance, if an application wants to be notified about an ethernet being received by a Network Interface Card (NIC), the application waits on a socket. This socket is a kernel construct that is filled by a NIC device driver after an IRQ is received which results in a notification of the application since the socket has new data.

This work focuses on extending the capabilities of the epoll mechanism present in Linux to also support being notified on events that occur in hardware devices. Epoll can be attached to different file descriptors to be informed of whether a certain event occurred. In case no events are available, the thread waits until events occur, which implies being notified by the thread that performs this event. This work will exemplarily focus on the event source in hardware being a ethernet packet being received by a NIC. The proof of concept should be implemented on a development platform based on the ZCU102 equipped with a 10G ethernet connection routed through the FPGA part of the Zynq MPSoC.

To successfully complete this work, you should have:

• first experience with embedded programming,
• very good programming skills in System Verilog,
• basic knowledge about Git,
• first experience with the Linux environment.

The student is expected to be highly motivated and independent.

Summary:
Current vehicle dynamics control systems regulate various vehicle state variables using classic PID control methods by comparing desired and actual states. The quality of such a controller can only be improved to a limited extent through parameter optimization, as the control is based solely on measured actual states. A conventional approach to solving this problem involves using a highly complex physical model to predict the future behavior of a signal based on known input parameters, thereby improving controller performance.
However, as such a model far exceeds the hardware limitations of a vehicle control unit, an alternative solution is to make predictions using a machine learning model. This research aims to investigate the feasibility and quality of such machine learning predictions and the resulting control loop quality using the example of motorcycle traction control.

Methodology:
The proposed methodology involves developing a time-series prediction approach,
potentially utilizing sequence-to-sequence classification, e.g., to determine the road
surface, tire types, loading conditions and other parameters as input for time series
prediction. To achieve this, various suitable model architectures (e.g., LSTM, GRU,
Transformer, Reservoir Computing) will be identified in the literature, and appropriate signals and datasets will be selected from existing vehicle data. The models will then be verified as open-loop in simulation, and the most suitable method and relevant data will be identified. If the simulation results are positive, the model will be implemented in a real-time hardware environment to test closed-loop performance.

Research Questions:

• Is predicting sensor signals possible using time-series prediction in an open-loop system?
• What data and model are necessary to enable robust prediction?
• Is control based on prediction possible in a closed-loop system?

The goal of this master thesis is to implement and evaluate various topologies for a NoI. This will be done using a chiplet design for Arm-based processors configured with a standardized C2C interface supporting cross chiplet cache coherency.

Future cars have a wide variety of sensors, such as cameras, LiDARs, and RADARs that generate a large amount of data. This data has to be sent via an intra-vehicular network (IVN) to further processing nodes, and, ultimately, actuators have to react to the sensor input. In between the processing steps, the intra-vehicular network has to ensure that all of the data and control signals reach their destination in time. Hence, next to a large amount of data, there are also strict timing constraints that the intra-vehicular network has to cope with. Therefore, the so-called time-sensitive networking (TSN) has been introduced. The functional safety of such networks plays an important role against the background of highly automated driving. Emerging errors have to be detected early and potential countermeasures have to be taken to keep the vehicle in a safe state. Therefore, highly sophisticated monitoring and diagnosis algorithms are a key requirement for future cars. (See Project EMDRIVE)

Project Description:

To test the functionality of the Monitoring Hardware, a functional chain implemented on 3 Aurix Boards is used for demonstration. The Aurix boards implement a chain of commands similar to an automotive application to reflect a real-life scenario, where the input feed will be from the Carla simulator. Based on the already existing work that implements a lane-keeping Assistant system, this system will integrate the Carla Simulator, which will take the input from the generated environment and send feedback commands about the direction of the car movement to support in-lane driving. It will also improve the functionality and efficiency of the system by using multiple CPUs and having stable Ethernet communication between multiple Aurix boards.

The substance of this work is to implement the following tasks:

1.  Bring up the Aurix boards, including the Aurix development environment.
2. Implement a functional chain consisting of (F1-F2-F3) that represents an Lane Keeping Assistant System.
3. Establish a stable communication between Aurix boards over the Ethernet switch.
4. Integrate Carla Simulator into the demonistration loop.
5. Use CPU0~CPU5 for more efficient task execution and system implementation. 

The primary skills that will be developed and needed during this project are the following:

• Good knowledge of C programming
• A solid understanding of System-on-Chip and the modules of general microcontroller
• A strong background on automotive application and system

Tracing events with hardware components is one powerful tool to monitor, debug, and improve existing designs. Through this approach, detailed insights can be acquired, and peak performance can be achieved, while being a challenging task to be integrated with good performance. One of the major challenges of tracing is to collect as much information as possible with ideally no impact on the to-be-analyzed system. Herewith, it can be ensured that the gained insights are representative of an execution without any tracing enabled. In this work, a hardware tracing component should be leveraged to reduce the intrusiveness of existing software tracing mechanisms in the Linux kernel. 

This should be integrated and tested on a hardware platform based on a Xilinx Zynq board. This features a heterogeneous ARM multicore setup directly integrated into the ASIC, combined with programmable logic in the FPGA part of the chip. In the FPGA a hardware accelerator is already implemented that should be traced with the new component.

To successfully complete this work, you should have:

• experience with microcontroller programming,
• basic knowledge about Git,
• first experience with the Linux environment.

The student is expected to be highly motivated and independent.

Linux is one of the most utilized Operating Systems in Embedded Systems and Cloud
Infrastructure worldwide. Sustainability will become more relevant in the future and saving power is a crucial aspect. This shows the increasing importance of efficient Linux Power Management.

The Power Management in Linux is implemented in several kernel subsystems correlating to hardware characteristics, like P-States (Frequency Scaling) and C-States (Sleep States). This thesis examines the Idle Power Management of Linux, and therefore focuses on C-States. C-States are per Core states and allow parts of the core to shut down individual features. Each processor implements C-States in different ways. Increasing C-State number, e.g. C6, translate to a deeper sleep with lower energy consumption and higher power-on reaction time.

The recently released eBPF functionality makes the kernel more programmable, bypassing the original monolithic characteristics. This mechanism can be divided into four components: the eBPF hooks in the kernel, the interfaces, the in-kernel eBPF infrastructure to execute eBPF bytecode and compile into native code and verify the code and finally the eBPF application itself, which can be written in a C like dialect and compiled into eBPF bytecode by LLVM and GCC.

This thesis aims to analyze and compare the idle governors in the current Kernel in specific situations. It also should provide insight in the C-State usage depending on the architecture. The data is acquired using specific Tracepoints within the Kernel, which can be recorded and parsed with the Kernel Tool perf. Furthermore, we explore the feasibility of a custom eBPF powered idle governor.