Michael Meidinger, M.Sc.

The goal of this master thesis is to implement and evaluate various topologies for a NoI. This will be done using a chiplet design for Arm-based processors configured with a standardized C2C interface supporting cross chiplet cache coherency.

The Compute Express Link (CXL) standard provides a high-performance interconnect between processors, memories, and accelerators. As an essential part of the Universal Chiplet Interconnect Express (UCIe) standard's protocol layer, it might become critical for advancements in chiplet-based architecture design. With high bandwidth, low latency, and coherence mechanisms, it is supposed to improve upon its PCIe foundation for applications with high requirements.
This seminar work should investigate how CXL and especially its three protocols (CXL.io, CXL.memory, CXL.cache) operate, how they compare to the PCIe baseline, and what a developer has to consider when employing CXL for a classical system-on-chip or a chiplet-based system.

Starting points for literature research could be the following papers:
https://ieeexplore.ieee.org/abstract/document/9912551
https://dl.acm.org/doi/abs/10.1145/3538643.3539745
https://dl.acm.org/doi/abs/10.1145/3624062.3624175

At LIS, we want to use the Duckietown hardware and software ecosystem to experiment with our reinforcement learning-based learning classifier tables (LCT) as part of the control system of the Duckiebots: https://www.ce.cit.tum.de/lis/forschung/aktuelle-projekte/duckietown-lab/.

More information on Duckietown can be found at https://www.duckietown.org/.

In this student work, we want to extend the bot's current abilities (lane following).

The goal of this work is to enable the bots to follow each other with a constant distance.
At the end, there should be a seamless integration in the Lane Following Pipeline.

• Knowledge about Image Processing
• Python

At LIS, we want to use the Duckietown hardware and software ecosystem to experiment with our reinforcement learning-based learning classifier tables (LCT) as part of the control system of the Duckiebots: https://www.ce.cit.tum.de/lis/forschung/aktuelle-projekte/duckietown-lab/.

More information on Duckietown can be found at https://www.duckietown.org/.

In this student work, we want to extend the bot's current abilities (lane following).

The goal of this work is to enable the bots to avoid obstacles on the road (e.g. ducks, other bots, ...) and to stop at intersections (red lines) for a predefined time.
At the end, there should be a seamless integration in the Lane Following Pipeline.

• Knowledge about Image Processing
• Python

Chiplet-based architectures are starting to become available, notably with the release of Intel’s Meteor Lake consumer CPUs at the end of last year. Even though most major players in the field are pursuing this strategy, there seems not to be a clear consensus yet on aspects like the chiplet-to-chiplet interconnect. The Universal Chiplet Interconnect Express (UCIe) standard appears to be a promising approach, but others are being developed, for example Bunch-of-Wires (BOW). In this seminar work, literature on chiplets should be investigated, specifically on topics as die-to-die interconnect or further challenges in the design of chiplet architectures.

Starting points for literature research could be the following papers:

https://ieeexplore.ieee.org/abstract/document/8416868

https://ieeexplore.ieee.org/abstract/document/9174651

https://ieeexplore.ieee.org/abstract/document/9893865

At LIS we want to use the Duckietown hardware and software ecosystem for experimenting with our reinforcement learning based learning classifier tables (LCT) as part of the control system of the Duckiebots: https://www.ce.cit.tum.de/lis/forschung/aktuelle-projekte/duckietown-lab/

More information on Duckietown can be found on https://www.duckietown.org/.

In this student work, we want to enable the use of the FPGA in the Lane Detection.
Previous work already experimented with the communication between NVIDIA Jetson and the FPGA via a DMA.

Goal of this work is to port the LSD to FPGA to benefit from offloading parts of the Lane Detection Alogithm from the CPU and execute them accelerated on the FPGA.
At the end, there should be a seamless integration in the Lane Following Pipeline.

• Knowledge about Image Processing
• Lots of FPGA experience
• VHDL
• Python