6G Future Lab Bavaria
6G Future Lab Bavaria is one of the first 6G-oriented research projects in Europe. It is funded by the Bavarian Ministry of Economic Affairs, Regional Development and Energy and it aims to explore approaches that tackle emerging problems in future generations of mobile communications. More information can be found in the project website: 6G Future Lab Bavaria
We at LIS are involved in the subproject TP7 together with our colleagues at LDV. Our goal is to develop fast, agile, ML-enhanced network node extensions.
Each network node consists of a control plane and a data plane. The control plane usually has a global view of the network state and reconfigures the data plane in a periodic or event-based manner in order to optimize various metrics, such as end-to-end latency and compute load. The data plane is responsible for processing incoming traffic and sending information to the control plane, such as notification of network congestion or statistics. The research at LIS focuses on developing architecture extensions in the data plane, which include
- a traffic splitter that either steers incoming packets to internal compute or memory units or forwards it to a neighbor node in the network,
- a remote DMA component that enables low-latency data transfer for context-based sevice migration, and
- a load monitoring unit that analyzes the incoming traffic and sends workload metrics to the control plane.
Implementation of a Packet-Processing Design on an FPGA
FlexRoute is a packet-processing architecture where offloads are arranged sequentially in the order that they are intended to be used. Each offload contains two forwarding channels in order to enable recirculation of packets through the sequence of offloads even when packets are coming back to back. It also consists of flexible forwarding logic that bypasses the corresponding processing units if their functionality is not needed by an incoming packet in order to reduce latency. Furthermore, it contains a scheduler that steers traffic to the least loaded processing unit and priority-aware traffic arbiters that privilege high-priority packets when traffic from multiple sources needs to exit the offload.
We have shown the potential benefit of our proposed design via cycle-accurate register-transfer level (RTL) simulations in Xilinx Vivado. The goal of this project is to synthesize and implement the design on an FPGA by using Vivado. Moreover, the design should be tested by injecting network traffic via Ethernet and measuring the throughput and the per-packet latency.
- Good knowledge of the basics of digital circuits, especially regarding timing analysis
- Experience with hardware description languages (HDL), such as VHDL or Verilog
- Preferably experience with electronic design automation (EDA) tools, such as Xilinx Vivado