This seminar will examine software-based Control-Flow Integrity (CFI) methods, focusing on techniques such as static analysis, compiler instrumentation, and runtime checks to enforce control-flow security at the program level. It will evaluate their advantages, including wide applicability and easier integration with existing systems, as well as limitations such as higher runtime overhead and potential precision issues. The seminar will also briefly compare these approaches with hardware-based CFI methods, emphasizing trade-offs between performance, security guarantees, and deployment complexity.

This seminar will explore hardware-based Control-Flow Integrity (CFI) methods, focusing on techniques such as shadow stacks, branch monitoring, and specialized instructions to enforce control-flow security at the processor level. It will analyze their benefits, including strong security guarantees and low runtime overhead, as well as drawbacks like hardware complexity and limited compatibility with legacy systems. The seminar will also briefly compare these methods with software-based CFI approaches, highlighting trade-offs such as flexibility versus performance and ease of deployment.

Static analysis plays an important role in understanding how software is expected to behave and in identifying potential defects early in the development process. While functional correctness can often be assessed statically, precise timing analysis is typically performed through dynamic methods, as execution time strongly depends on architectural features and shared hardware resources that influence temporal behavior.

Nevertheless, even when abstracting from certain dynamic effects—such as shared resource contention and detailed memory access behavior—it is possible to estimate the number of processor cycles required to execute a given sequence of instructions, provided that the target architecture is well understood. Hardware simulators such as Spike or gem5 follow this principle by modeling processor behavior to approximate execution timing.

The objective of this thesis is to develop a tool that estimates the cycle count required to execute specific instruction sequences on Infineon’s TriCore architecture. The focus will be on modeling the architectural pipelines, taking into account their structure, parallelism capabilities, and constraints. In particular, the work will analyze how different pipeline configurations influence instruction throughput and latency, as well as the benefits and limitations introduced by the multi-pipeline design.

Voraussetzungen