Static analysis plays an important role in understanding how software is expected to behave and in identifying potential defects early in the development process. While functional correctness can often be assessed statically, precise timing analysis is typically performed through dynamic methods, as execution time strongly depends on architectural features and shared hardware resources that influence temporal behavior.

Nevertheless, even when abstracting from certain dynamic effects—such as shared resource contention and detailed memory access behavior—it is possible to estimate the number of processor cycles required to execute a given sequence of instructions, provided that the target architecture is well understood. Hardware simulators such as Spike or gem5 follow this principle by modeling processor behavior to approximate execution timing.

The objective of this thesis is to develop a tool that estimates the cycle count required to execute specific instruction sequences on Infineon’s TriCore architecture. The focus will be on modeling the architectural pipelines, taking into account their structure, parallelism capabilities, and constraints. In particular, the work will analyze how different pipeline configurations influence instruction throughput and latency, as well as the benefits and limitations introduced by the multi-pipeline design.

Voraussetzungen