Ensuring memory safety is a critical challenge in embedded systems, particularly in resource-constrained environments such as microcontrollers. Buffer overflows remain a common source of vulnerabilities and unexpected behavior. Execution traces provide a detailed view of runtime behavior and offer a potential basis for detecting such issues without intrusive instrumentation.

The goal of this thesis is to investigate the feasibility of detecting buffer overflows through the analysis of execution traces, assuming prior knowledge of the executing program and access to its corresponding ELF file. The work aims to define a focused and practical approach suitable for a bachelor’s thesis.

Approach:

The proposed method will combine static and dynamic analysis:

• Static Analysis:

Extract memory layout information from the ELF file, particularly the size and location of global variables.

• Dynamic Trace Analysis:

Analyze execution traces to reconstruct memory access patterns during runtime.

• Heap and Stack Inference:

Develop methods to infer heap and stack boundaries and usage dynamically from trace data, as this information is not directly available.

• Buffer Overflow Detection:

Identify deviations from expected memory access patterns that may indicate buffer overflows.

• Trace Filtering and Reduction:

Design techniques to filter and reduce the volume of trace data to ensure tractability and efficiency of the analysis.

Expected Outcomes:

• A clearly defined methodology for detecting buffer overflows using execution traces

• A prototype implementation demonstrating the approach

• An evaluation of feasibility, limitations, and potential accuracy of the method

Prerequisites

Static analysis plays an important role in understanding how software is expected to behave and in identifying potential defects early in the development process. While functional correctness can often be assessed statically, precise timing analysis is typically performed through dynamic methods, as execution time strongly depends on architectural features and shared hardware resources that influence temporal behavior.

Nevertheless, even when abstracting from certain dynamic effects—such as shared resource contention and detailed memory access behavior—it is possible to estimate the number of processor cycles required to execute a given sequence of instructions, provided that the target architecture is well understood. Hardware simulators such as Spike or gem5 follow this principle by modeling processor behavior to approximate execution timing.

The objective of this thesis is to develop a tool that estimates the cycle count required to execute specific instruction sequences on Infineon’s TriCore architecture. The focus will be on modeling the architectural pipelines, taking into account their structure, parallelism capabilities, and constraints. In particular, the work will analyze how different pipeline configurations influence instruction throughput and latency, as well as the benefits and limitations introduced by the multi-pipeline design.

Prerequisites