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Prioritization Algorithms for a Page Preloading Mechanism
Beschreibung
A non-invasive performance monitoring module counter will be developed to evaluate memory prefetcher behavior at the last-level of cache. It will observe prefetch operations without altering system functionality or timing, ensuring accurate measurement of workload characteristics. Configurable counters will capture metrics like bandwidth usage, prefetch coverage, accuracy, and hit/miss ratios, in real time. The module will be implemented on an FPGA together with the rest of the system, and an available communication interface will be used to send the collected data to the attached PC. On the host side, a dedicated application will receive metric streams and update interactive dashboards, that will render live plots illustrating performance trends. Such visualization will facilitate intuitive analysis and real-time insights during live demonstrations under realistic workload conditions, and also help make future architectural decisions. The design of the module will keep in mind future expansion, leaving room for integration of additional performance metrics and advanced analysis capabilities. By combining hardware-based data collection with a flexible host application, the project will deliver a robust tool for cache prefetcher evaluation.
Voraussetzungen
- Strong Experience with VHDL Coding
- Basic Knowledge is C Programmng
- Basic knowledge on MPSoC, cache hierarchies etc.
- B.Sc. in Electrical Engineering or similar
Kontakt
Oliver Lenke
o.lenke@tum.de
Betreuer:
Student
SmartNIC Hardware Extensions for Server State Tracking
Beschreibung
With the advent of research on the next generation of
mobile communications 6G, we are engaged in exploring
architecture extensions for Smart Network Interface Cards
(SmartNICs). To enable adaptive, energy-efficient and
low-latency network interfaces, we are prototyping a
custom packet processing pipeline on FPGA-based NICs,
partially based on the open-nic project
(https://github.com/Xilinx/open-nic).
To improve the performance and energy efficiency of a
modern server, SmartNICs can be used to preprocess
incoming packets and gather characteristics on traffic and processing requirements. This information can be used to change the processing behavior of the server and react to the dynamic network and processing requirements. Hereby, a decisive task is the performant and accurate tracking of key metrics to characterize the current state of the server, both regarding the incoming traffic and the computational aspects in the processing resources of the server.
The goal of this work is to implement monitoring logic for key metrics, such as packet arrival rate, pipeline utilization, queue fill levels, etc. as hardware extensions in the SmartNIC using HDL. A key research question of this work targets finding out how accurate tracking of the CPU utilization is possible in the SmartNIC with minimal software-side intrusiveness. A useful tool for future proof and software-defined networking processing in the SmartNIC is the P4 framework. Therefore, a possible integration of the developed monitoring output into the P4 framework (as "externs") should be further evaluated. This should be accompanied by a P4 runtime in software to control the hardware pipeline in an asynchronous manner over longer timespans.
Voraussetzungen
- Programming skills in VHDL/Verilog, C and preferably P4 (and Python)
- Practical experience with FPGA Design and Implementation
- Good Knowledge of computer architecture, low-level software and OSI network model
- Comfortable with the Linux command line and bash
Kontakt
Marco Liess, M. Sc.
Tel.: +49.89.289.23873
Email: marco.liess@tum.de