Zafer Attal, M.Sc.

Sporadic anomalies in automotive systems can degrade performance over time and may originate from various system components. In automotive applications, anomalies are often observed at the sensor and ECU levels, with potential propagation through the in-vehicle network via Ethernet. Such anomalies may be the result of deviations in electronic control units, highlighting the importance of monitoring these signals over Ethernet.

Not all processing anomalies are equally detectable over Ethernet due to inherent limitations in the monitoring techniques and the nature of the anomalies. This seminar will explore various anomaly categories, investigate their potential causes, and assess the likelihood of their propagation through the network.

The goal of this seminar is to provide a comprehensive analysis of these anomaly categories, evaluate the underlying causes, and discuss the potential for their detection and mitigation when monitored over Ethernet.

Sporadic anomalies in automotive systems can degrade performance over time and may originate from various system components. In automotive applications, anomalies are often observed at the sensor and ECU levels, with potential propagation through the in-vehicle network via Ethernet. Such anomalies may be the result of deviations in electronic control units, highlighting the importance of monitoring these signals over Ethernet.

Not all processing anomalies are equally detectable over Ethernet due to inherent limitations in the monitoring techniques and the nature of the anomalies. This seminar will explore various anomaly categories, investigate their potential causes, and assess the likelihood of their propagation through the network.

The goal of this seminar is to provide a comprehensive analysis of these anomaly categories, evaluate the underlying causes, and discuss the potential for their detection and mitigation when monitored over Ethernet.

In today’s data-driven world, processing approaches are typically divided between cloud-based solutions—with virtually unlimited resources—and localized processing, which is constrained by hardware limitations. While the cloud offers extensive computational power, localized processing is often required for real-time applications where latency and data security are critical concerns.

To bridge this gap, various algorithms have been developed to pre-process data or extract essential information before it is sent to the cloud.

The goal of this seminar is to explore and compare these algorithms, evaluating their computational load on local hardware and their overall impact on system performance.

About the Project
Modern vehicles rely on complex distributed systems and generate extensive runtime data from ECUs and in-vehicle networks. These data streams must be analyzed effectively to detect sporadic anomalies. The Diagnosis Unit (DU) currently has no integration with the cloud, which limits the possibility of remote configuration and coordination of local DU during runtime. In highly automated vehicles, real-time anomaly diagnosis is essential for safety, reliability, and early intervention. The current Diagnosis Unit (DU) architecture detects anomalies via Ethernet snooping and trace monitoring but lacks embedded intelligence to autonomously categorize anomalies.

Project Description
This thesis aims to bridge that gap by developing and deploying a lightweight Machine Learning classifier capable of locally identifying the type of anomaly based on metadata (e.g., message rates, ID sequences) and trace-level indicators (e.g., control flow deviations, instruction durations, executed functions). The classifier must be tailored for low-power, runtime embedded systems like the ZCU102 board, ensuring it meets latency, memory, and CPU constraints.

The key tasks for this internship include:

• Build an anomaly classification dataset using real and synthetic traces. 
• Design a minimal-overhead classifier suitable for embedded edge platforms. 
• Compare classification techniques (e.g., decision trees, TinyML NNs, rule-based logic). 
• Optimize the model for execution speed and memory footprint. 
• Integrate and validate the classifier within the DU software stack. 
• Quantitatively evaluate accuracy, timing, and resource utilization under realistic conditions

Key Responsibilities: 

•  Dataset Generation: Create labeled datasets using synthetic trace injections and logged anomaly traces from Aurix boards. 
• Model Development: ? Design candidate classifiers using scikit-learn and/or TensorFlow Lite for Microcontrollers. ? Evaluate trade-offs: accuracy vs. latency vs. Footprint.
• Embedded Integration: ? Port the final model to C/C++ for execution on the DU Processing System (Linux). ? Interface classifier with DU anomaly metadata and trace analyzer. 
• Evaluation: ? Test classifier on live or replayed data. ? Measure detection latency, false positives/negatives, inference time, and CPU/RAM usage. 
• Reporting & Documentation: ? Document training pipeline, performance evaluation, and embedded integration. ? Prepare thesis manuscript and possibly a conference/poster paper.

Voraussetzungen

Future cars rely on a wide variety of sensors—including cameras, LiDARs, and RADARs—that generate enormous amounts of data. This data flows through the intra-vehicular network (IVN) to processing nodes, ultimately triggering actuators. With strict timing constraints essential for vehicle safety, time-sensitive networking (TSN) is now a critical component in modern automotive systems. Within the context of the EMDRIVE project, our team is developing new monitoring and diagnostic approaches to detect errors early and maintain functional safety in highly automated driving environments.

Project Description

This project focuses on developing a synchronization mechanism between the anomaly detection unit in the ZCU102 PL (FPGA) and the Aurix TC397 ECU’s trace system (MCDS). The goal is to ensure that communication anomalies detected in the PL are tightly aligned with ECU trace captures, so that the limited 2 MB trace buffer contains the most relevant execution history. By achieving low-latency triggering and global timestamp consistency, the Diagnosis Unit (DU) can accurately correlate network-level and processing-level anomalies. 

The key tasks include:

• Design and implement a low-latency handshake (PL → Aurix) using GPIO/interrupts or timestamp markers. 
• Evaluate and compare synchronization methods: hardware trigger line vs. shared global clock (PTP/PS counter). 
• Modify the Aurix side (via TAS or external interrupt) to latch triggers and freeze/stop tracing instantly. 
• Validate synchronization accuracy by measuring drift and latency between PL anomalies and ECU trace entries. 
• Integrate synchronization metadata into DU anomaly reports. 
• Allow circular trace buffer filling instead of continouse trace transfer.

Key Responsibilities:

• Collaborate with interdisciplinary teams to integrate and test the complete system.
• Develop and integrate a PL module for trigger/timestamp generation. 
• Extend TAS/PS software to handle trace stop commands upon triggers. 
• Configure Aurix trace system (MCDS) to respond to triggers or timestamps. 
• Perform experiments and validation with injected anomalies to measure synchronization precision. 
• Document the synchronization design and provide usage guidelines for future DU setups.

Voraussetzungen

Modern vehicles rely on complex distributed systems and generate extensive runtime data from ECUs and invehicle networks. These data streams must be analyzed effectively to detect sporadic anomalies. The Diagnosis Unit (DU) currently includes trace buffering capabilities, but its efficiency is limited due to static configuration.

Project Description

The primary goal of this project is to migrate existing software packages—used to record ECU traces and analyze processing anomalies—onto the ZCU102 board. This migration will enable local processing of anomalies and establish a robust PS/PL interface between the anomaly detection hardware (implemented on the FPGA) and the processing system running the software. This project aims to optimize trace buffer configurations to improve runtime anomaly detection and diagnosis. The goal is to develop a configurable system that adjusts trace window sizes and recording parameters based on anomaly type and timing requirements.

The key tasks include:

• Empirical Trace Profiling: Identify trace coverage requirements for various anomaly types.
• Buffer Strategy Design: Develop dynamic buffer sizing algorithms with adjustable granularity.
• Trace Window Configuration: Implement software logic for buffer allocation and pre/post-event capture.
• Evaluation and Benchmarking: Measure coverage accuracy, memory usage, bandwidth requirements and response latency under different configurations.

Key Responsibilities:

• Analyze DU’s current trace subsystem to understand performance limits.
• Design experiments using ZCU102 and Aurix testbeds to test trace configurations.
• Develop a parameterized buffer control interface.
• Conduct real-time tests with injected anomalies and record performance metrics.
• Document findings and propose recommended buffer policies.

Voraussetzungen

About the Project:
Future cars rely on a wide variety of sensors—including cameras, LiDARs, and RADARs—that generate enormous amounts of data. This data flows through the intra-vehicular network (IVN) to processing nodes, ultimately triggering actuators. With strict timing constraints essential for vehicle safety, time-sensitive networking (TSN) is now a critical component in modern automotive systems. Within the context of the EMDRIVE project, our team is developing new monitoring and diagnostic approaches to detect errors early and maintain functional safety in highly automated driving environments.

Project Description:
The primary goal of this project is to migrate existing software packages—used to record ECU traces and analyze processing anomalies—onto the ZCU102 board. This migration will enable local processing of anomalies and establish a robust PS/PL interface between the anomaly detection hardware (implemented on the FPGA) and the processing system running the software.

The key tasks include:

• TAS Tool Configuration: Bring up the TAS tool and configure it to work with the Multi Core Debug Solution (MCDS) for trace recording.

• Trace Analyzer Deployment: Bring up and configure the Trace Analyzer to parse recorded traces and detect deviations in processing.

• Software Migration: Migrate the existing software packages to run on the Processing System (PS) of the ZCU102 board.

• Interface Integration: Develop and integrate a stable interface between the Programmable Logic (PL) and the PS, ensuring efficient sharing of data, status, and configuration information.

Key Responsibilities:

• Analyze existing software packages and understand the hardware integration requirements.
• Configure and validate both the TAS tool and the Trace Analyzer.
• Adapt and optimize software for deployment on the ZCU102 board.
• Develop and implement a robust PS/PL interface for seamless communication between hardware and software.
• Collaborate with interdisciplinary teams to integrate and test the complete system.

Voraussetzungen

In today’s data-driven world, processing approaches are typically divided between cloud-based solutions—with virtually unlimited resources—and localized processing, which is constrained by hardware limitations. While the cloud offers extensive computational power, localized processing is often required for real-time applications where latency and data security are critical concerns.

To bridge this gap, various algorithms have been developed to pre-process data or extract essential information before it is sent to the cloud.

The goal of this seminar is to explore and compare these algorithms, evaluating their computational load on local hardware and their overall impact on system performance.