Zafer Attal, M.Sc.
Wissenschaftlicher Mitarbeiter
Technische Universität München
TUM School of Computation, Information and Technology
Lehrstuhl für Integrierte Systeme
Arcisstr. 21
80290 München
Tel.: +49.89.289.23853
Fax: +49.89.289.28323
Gebäude: N1 (Theresienstr. 90)
Raum: N2138
Email: zafer.attal(at)tum.de
Curriculum Vitae
Education
- 2019 - 2022 Master of Science in Communication Engineering, Technical University of Munich, Munich, Germany
- 2015 - 2019 Bachelor of Science in Electrical and Electronics Engineering, Middle East Technical University, Turkey
Work Experience
- 2024-present PhD student at the Chair of Integrated Systems, Technical University of Munich, Munich, Germany
- 2022 - 2023 Graphics System Design Engineer, Infineon Technologies, Munich, Germany
Research
Available Work
Ongoing Work
Design and Deployment of a Lightweight On-Device Classifier for ECU Anomaly Categorization
Beschreibung
About the Project
Modern vehicles rely on complex distributed systems and generate extensive runtime data from ECUs and in-vehicle networks. These data streams must be analyzed effectively to detect sporadic anomalies. The Diagnosis Unit (DU) currently has no integration with the cloud, which limits the possibility of remote configuration and coordination of local DU during runtime. In highly automated vehicles, real-time anomaly diagnosis is essential for safety, reliability, and early intervention. The current Diagnosis Unit (DU) architecture detects anomalies via Ethernet snooping and trace monitoring but lacks embedded intelligence to autonomously categorize anomalies.
Project Description
This thesis aims to bridge that gap by developing and deploying a lightweight Machine Learning classifier capable of locally identifying the type of anomaly based on metadata (e.g., message rates, ID sequences) and trace-level indicators (e.g., control flow deviations, instruction durations, executed functions). The classifier must be tailored for low-power, runtime embedded systems like the ZCU102 board, ensuring it meets latency, memory, and CPU constraints.
The key tasks for this internship include:
- Build an anomaly classification dataset using real and synthetic traces.
- Design a minimal-overhead classifier suitable for embedded edge platforms.
- Compare classification techniques (e.g., decision trees, TinyML NNs, rule-based logic).
- Optimize the model for execution speed and memory footprint.
- Integrate and validate the classifier within the DU software stack.
- Quantitatively evaluate accuracy, timing, and resource utilization under realistic conditions
Key Responsibilities:
- Dataset Generation: Create labeled datasets using synthetic trace injections and logged anomaly traces from Aurix boards.
- Model Development: ? Design candidate classifiers using scikit-learn and/or TensorFlow Lite for Microcontrollers. ? Evaluate trade-offs: accuracy vs. latency vs. Footprint.
- Embedded Integration: ? Port the final model to C/C++ for execution on the DU Processing System (Linux). ? Interface classifier with DU anomaly metadata and trace analyzer.
- Evaluation: ? Test classifier on live or replayed data. ? Measure detection latency, false positives/negatives, inference time, and CPU/RAM usage.
- Reporting & Documentation: ? Document training pipeline, performance evaluation, and embedded integration. ? Prepare thesis manuscript and possibly a conference/poster paper.
Voraussetzungen
Required Skills:
- Proficiency in Python and C/C++.
- Solid understanding of classification algorithms and ML evaluation metrics.
- Knowledge of real-time systems, SoC platforms, or embedded diagnostics.
- Familiarity with Linux-based systems, cross-compilation, and performance profiling.
- (Optional) Experience with Zynq boards, TinyML, or vehicle diagnostics.
Expected Deliverables:
- A functioning, embedded ML-based classification module for the DU.
- Labeled dataset and training pipeline.
- Comprehensive performance report (accuracy, timing, and system load).
- Integration with DU demonstrator showing real-time anomaly categorization.
- Final thesis manuscript and presentation.
Benefits:
- Direct impact on enhancing autonomous diagnosis in smart automotive systems.
- Hands-on deployment of real ML models in embedded systems.
- Contribute to the first intelligent self-assessing DU prototype.
- Potential for academic publication or continuation into research/industry projects.
Kontakt
Zafer Attal
zafer.attal@tum.de
Betreuer:
Time Synchronization & Trigger Coordination between communication anomaly detection and trace retrieval
Beschreibung
Future cars rely on a wide variety of sensors—including cameras, LiDARs, and RADARs—that generate enormous amounts of data. This data flows through the intra-vehicular network (IVN) to processing nodes, ultimately triggering actuators. With strict timing constraints essential for vehicle safety, time-sensitive networking (TSN) is now a critical component in modern automotive systems. Within the context of the EMDRIVE project, our team is developing new monitoring and diagnostic approaches to detect errors early and maintain functional safety in highly automated driving environments.
Project Description
This project focuses on developing a synchronization mechanism between the anomaly detection unit in the ZCU102 PL (FPGA) and the Aurix TC397 ECU’s trace system (MCDS). The goal is to ensure that communication anomalies detected in the PL are tightly aligned with ECU trace captures, so that the limited 2 MB trace buffer contains the most relevant execution history. By achieving low-latency triggering and global timestamp consistency, the Diagnosis Unit (DU) can accurately correlate network-level and processing-level anomalies.
The key tasks include:
- Design and implement a low-latency handshake (PL → Aurix) using GPIO/interrupts or timestamp markers.
- Evaluate and compare synchronization methods: hardware trigger line vs. shared global clock (PTP/PS counter).
- Modify the Aurix side (via TAS or external interrupt) to latch triggers and freeze/stop tracing instantly.
- Validate synchronization accuracy by measuring drift and latency between PL anomalies and ECU trace entries.
- Integrate synchronization metadata into DU anomaly reports.
- Allow circular trace buffer filling instead of continouse trace transfer.
Key Responsibilities:
- Collaborate with interdisciplinary teams to integrate and test the complete system.
- Develop and integrate a PL module for trigger/timestamp generation.
- Extend TAS/PS software to handle trace stop commands upon triggers.
- Configure Aurix trace system (MCDS) to respond to triggers or timestamps.
- Perform experiments and validation with injected anomalies to measure synchronization precision.
- Document the synchronization design and provide usage guidelines for future DU setups.
Voraussetzungen
Required Skills:
- Digital design knowledge (FPGA/PL) and Verilog/VHDL or HLS.
- Embedded C/C++ programming for Aurix TC397 (MCDS configuration) and Zynq PS.
- Familiarity with synchronization protocols (interrupt handling, timestamping, PTP).
- Skills in measurement/validation setups (logic analyzers, latency measurement).
- Basic knowledge of automotive IVN diagnostics is beneficial.
Benefits:
- Hands-on experience with hardware-software synchronization in real automotive ECUs.
- Deep understanding of PL ↔ PS ↔ ECU interaction (critical in modern heterogeneous SoCs).
- Contribution to improving accuracy and reliability of the Diagnosis Unit’s anomaly detection.
- Opportunity to validate and publish real-time synchronization results in research/industry contexts.
- Practical learning that directly applies to automotive gateway/NIC design.
Kontakt
Zafer Attal
Chair of Integrated Systems
Arcisstraße 21, 80333 Munich
Tel. +49 89 289 23853
zafer.attal@tum.de
www.lis.ei.tum.de
Betreuer:
Adaptive Trace Buffer Configuration for Effective ECU Anomaly Detection & Diagnosis
Beschreibung
Modern vehicles rely on complex distributed systems and generate extensive runtime data from ECUs and invehicle networks. These data streams must be analyzed effectively to detect sporadic anomalies. The Diagnosis Unit (DU) currently includes trace buffering capabilities, but its efficiency is limited due to static configuration.
Project Description
The primary goal of this project is to migrate existing software packages—used to record ECU traces and analyze processing anomalies—onto the ZCU102 board. This migration will enable local processing of anomalies and establish a robust PS/PL interface between the anomaly detection hardware (implemented on the FPGA) and the processing system running the software. This project aims to optimize trace buffer configurations to improve runtime anomaly detection and diagnosis. The goal is to develop a configurable system that adjusts trace window sizes and recording parameters based on anomaly type and timing requirements.
The key tasks include:
- Empirical Trace Profiling: Identify trace coverage requirements for various anomaly types.
- Buffer Strategy Design: Develop dynamic buffer sizing algorithms with adjustable granularity.
- Trace Window Configuration: Implement software logic for buffer allocation and pre/post-event capture.
- Evaluation and Benchmarking: Measure coverage accuracy, memory usage, bandwidth requirements and response latency under different configurations.
Key Responsibilities:
- Analyze DU’s current trace subsystem to understand performance limits.
- Design experiments using ZCU102 and Aurix testbeds to test trace configurations.
- Develop a parameterized buffer control interface.
- Conduct real-time tests with injected anomalies and record performance metrics.
- Document findings and propose recommended buffer policies.
Voraussetzungen
Required Skills:
- Proficiency in C/C++ or Python programming skills.
- Strong understanding of System-on-Chip (SoC) architectures and microcontroller modules.
- Understanding of embedded systems and trace logging.
- Familiarity with automotive ECUs and microcontroller architecture.
- Familiarity with Linux-based systems and FPGA integration is a plus.
Benefits:
- Deep understanding of runtime embedded diagnostics.
- Work with high-performance SoCs and automotive microcontrollers.
- Hands-on experience in optimizing embedded data capture pipelines.
- Contribution to scalable and robust in-vehicle diagnostic systems.
Kontakt
Zafer Attal
zafer.attal@tum.de
Betreuer:
Localizing Automotive Diagnostic Solutions: Software Migration and PS/PL Interface Implementation on ZCU102
Beschreibung
About the Project:
Future cars rely on a wide variety of sensors—including cameras, LiDARs, and RADARs—that generate enormous amounts of data. This data flows through the intra-vehicular network (IVN) to processing nodes, ultimately triggering actuators. With strict timing constraints essential for vehicle safety, time-sensitive networking (TSN) is now a critical component in modern automotive systems. Within the context of the EMDRIVE project, our team is developing new monitoring and diagnostic approaches to detect errors early and maintain functional safety in highly automated driving environments.
Project Description:
The primary goal of this project is to migrate existing software packages—used to record ECU traces and analyze processing anomalies—onto the ZCU102 board. This migration will enable local processing of anomalies and establish a robust PS/PL interface between the anomaly detection hardware (implemented on the FPGA) and the processing system running the software.
The key tasks include:
-
TAS Tool Configuration: Bring up the TAS tool and configure it to work with the Multi Core Debug Solution (MCDS) for trace recording.
-
Trace Analyzer Deployment: Bring up and configure the Trace Analyzer to parse recorded traces and detect deviations in processing.
-
Software Migration: Migrate the existing software packages to run on the Processing System (PS) of the ZCU102 board.
-
Interface Integration: Develop and integrate a stable interface between the Programmable Logic (PL) and the PS, ensuring efficient sharing of data, status, and configuration information.
Key Responsibilities:
- Analyze existing software packages and understand the hardware integration requirements.
- Configure and validate both the TAS tool and the Trace Analyzer.
- Adapt and optimize software for deployment on the ZCU102 board.
- Develop and implement a robust PS/PL interface for seamless communication between hardware and software.
- Collaborate with interdisciplinary teams to integrate and test the complete system.
Voraussetzungen
Required Skills:
- Proficiency in C programming.
- Strong understanding of System-on-Chip (SoC) architectures and microcontroller modules.
- Background in automotive applications and systems.
- Experience with hardware description languages (e.g., VHDL) and embedded systems (preferred).
- Familiarity with Linux-based systems and FPGA integration is a plus.
Benefits:
- Hands-on experience with cutting-edge automotive diagnostic technology.
- Exposure to advanced hardware-software integration and embedded systems.
- Opportunity to contribute to projects that enhance the safety and reliability of future vehicles.
- Collaborative work environment with industry-leading partners.
Kontakt
Zafer Attal
zafer.attal@tum.de
Betreuer:
Completed Work
Kontakt
Zafer Attal
zafer.attal@tum.de
Betreuer:
Kontakt
zafer.attal@tum.de
Betreuer:
Student
Kontakt
zafer.attal@tum.de
Betreuer:
Student
Kontakt
zafer.attal@tum.de
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Publication
2025
- An Approach for Automotive ECU Diagnosis via Ethernet Snooping & Microcontroller Tracing. 28th Euromicro Conference Series on Digital System Design (DSD) 2025, 2025 mehr… BibTeX Volltext ( DOI )