Oliver Lenke, M.Sc.

Memory prefetching is a common technique used to hide memory access latencies and improve the performance of MPSoC architectures. In contrast to caches, data is read from the DRAM and stored in a fast on-chip buffer ahead of the actual CPU load request.

Such a memory prefetching mechanism is part of the TUM contribution to the CeCaS project and is currently under development. Besides a simulation environment, an FPGA-based prototype implementation was directly integrated into a State-of-the-Art MPSoC design.

The goal of this thesis is to develop a baremetal test environment for this preloading module to evaluate all possible testcases. The testenvironment will be developed in a hardware-related C programming style and can be executed directly on the FPGA prototype platform as well as on a cycle-accurate VHDL simulation.

Toward this goal, you will complete the following tasks:
1. Understanding the existing Memory Access and Preloading mechanism
2. Explore and understand possible corner-case scenarios
3. Develop a baremetal C program that triggers all corner cases
4. Analyse and discuss the results

Voraussetzungen

Cache controllers play a crucial role in bridging the performance gap between fast CPU cores and comparatively slow main memory. As the central management units of cache hierarchies, they are responsible for handling memory requests, maintaining data consistency, and optimizing data placement and replacement policies.

Modern cache controllers must balance multiple, often conflicting, design goals — including low latency, high throughput, power efficiency, and scalability in multi-core environments. To achieve this, they implement a wide range of optimization techniques at both the architectural and microarchitectural levels.

This seminar focuses on the structure, operation, and optimization techniques of cache controllers. Topics of interest include cache replacement and writeback strategies, prefetching mechanisms, and adaptive policies for latency reduction and energy savings. Other potential areas include dynamic cache partitioning, way prediction, and the use of machine learning techniques for cache management decisions.

The goal of this seminar is to study and compare different cache controller designs and optimization approaches, evaluate their impact on performance, and discuss emerging trends in cache hierarchy design for modern CPUs and heterogeneous architectures.

A set of introductory materials and selected research papers will be provided as a starting point.

Voraussetzungen

As DRAM technology continues to scale down, the physical proximity of memory cells has led to new types of reliability and security challenges. One of the most prominent examples is the Rowhammer effect — a hardware vulnerability that allows an attacker to induce bit flips in adjacent memory rows by repeatedly activating (“hammering”) specific rows at high frequency.

Rowhammer attacks exploit this phenomenon to manipulate data in memory without direct access privileges, potentially bypassing system and software-level protections. Over the past decade, a variety of Rowhammer-based exploits have been demonstrated, affecting systems from personal computers to cloud servers and mobile devices.

This seminar focuses on the mechanisms, implications, and countermeasures of Rowhammer attacks. Participants will study the physical and architectural causes of Rowhammer, survey known attack variants and analyze hardware-based prevention strategies. Possible aspects include error-correcting codes (ECC), targeted refresh mechanisms, memory access monitoring, probabilistic row activation, and architectural redesigns in DRAM controllers.

The goal of this seminar is to compare different mitigation approaches, evaluate their effectiveness, and discuss ongoing research trends in securing modern memory systems against Rowhammer-like vulnerabilities.

A selection of introductory and research literature will be provided as a starting point.

Voraussetzungen

DRAM controllers are key components in modern computer systems, serving as the interface between the processor and main memory. Their primary responsibilities include coordinating memory access operations, minimizing access latency, and maintaining data integrity.

A DRAM controller manages read and write operations, address translation, scheduling of concurrent memory requests, and the periodic refresh of DRAM cells. As memory latency and bandwidth limitations increasingly become performance bottlenecks, the design and optimization of DRAM controllers play a crucial role in achieving high system performance.

This seminar focuses on the architecture, operation, and optimization techniques of DRAM controllers. Possible topics include command scheduling, access prediction, power management, quality of service (QoS) in shared memory systems, as well as the integration of caches or prefetching mechanisms within the controller. The goal is to study and compare different controller designs, analyze their advantages, and discuss typical use cases.

An introduction to the fundamental concepts and selected literature will be provided.

Voraussetzungen

Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density make DRAM omnipresend in most computer architectures. However, DRAM accesses are rather slow and require a dedicated DRAM controller
that coordinates the read and write accesses to the DRAM as well as the refresh cycles. In order to reduce the DRAM access latency, memory prefetching is a common technique to access data prior to their actual usage. However, this requires sophisticated prediction algorithms in order to prefetch the right data at the right time.

The Goal of this thesis is to refine an existing DRAM preloading mechanism on an FPGA based prototype platform. It should be able to preload different pages alternatively and dynamically switch between two pages. This requires sophisticated changes in several components, FSMs and the Tag Memory of the hardware preload unit.

Towards this goal, you'll complete the following tasks:
1. Understanding the existing Memory Access and Preloading mechanism
2. VHDL implementation of the refined preloading functionalities
3. Write and execute small baremetal test programs
4. Analyse and discuss the performance results

Voraussetzungen

We are developing a dynamically configurable preload and crypto unit.
Specifically, this means two features: preload and/or dynamic activation/deactivation via software write AND self-adaptive burst length when the decryptor is disabled, otherwise fixed at 64B.
This requires, as discussed, routing the AXI ID to the memory controller, thus enabling stream separation of memory addresses (multicore aspect), and, on the other hand, providing a memory-mapped interface to the CPU.
We will then use this framework to further develop the priority mechanism.
This mechanism has two scientifically interesting features: separate prioritization for each core, arbitration between different cores, for example, based on access frequency, and possibly also externally configurable (e.g., one core is running a particularly important application, which is already determined in advance)
This allows to switch between a self-adaptive process and a user-configurable operation mode.
Optionally, you can also extrapolate additional pages and include them in the prioritization as well.

Voraussetzungen

Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density make DRAM omnipresend in most computer architectures. However, DRAM accesses are rather slow and require a dedicated DRAM controller
that coordinates the read and write accesses to the DRAM as well as the refresh cycles. In order to reduce the DRAM access latency, memory prefetching is a common technique to access data prior to their actual usage. However, this requires sophisticated prediction algorithms in order to prefetch the right data at the right time.

The Goal of this thesis is to transfer an existing DRAM preloading mechanism to an FPGA based prototype platform of the RISC-V CVA6 architecture. This requires a profund understanding of AHB and AXI communication protocolls as well as the functionalities of the cache and memory hierarchie of an MPSoC system.

Towards this goal, you'll complete the following tasks:
1. Understanding the existing Memory Access and Preloading mechanism
2. VHDL implementation of the refined preloading functionalities
3. Write and execute small baremetal test programs
4. Analyse and discuss the performance results

Voraussetzungen

A non-invasive performance monitoring module counter will be developed to evaluate memory prefetcher behavior at the last-level of cache. It will observe prefetch operations without altering system functionality or timing, ensuring accurate measurement of workload characteristics. Configurable counters will capture metrics like bandwidth usage, prefetch coverage, accuracy, and hit/miss ratios, in real time. The module will be implemented on an FPGA together with the rest of the system, and an available communication interface will be used to send the collected data to the attached PC. On the host side, a dedicated application will receive metric streams and update interactive dashboards, that will render live plots illustrating performance trends. Such visualization will facilitate intuitive analysis and real-time insights during live demonstrations under realistic workload conditions, and also help make future architectural decisions. The design of the module will keep in mind future expansion, leaving room for integration of additional performance metrics and advanced analysis capabilities. By combining hardware-based data collection with a flexible host application, the project will deliver a robust tool for cache prefetcher evaluation. 

Voraussetzungen