Oliver Lenke, M.Sc.
Wissenschaftlicher Mitarbeiter
Technische Universität München
TUM School of Computation, Information and Technology
Lehrstuhl für Integrierte Systeme
Arcisstr. 21
80333 München
Tel.: +49.89.289.28387
Fax: +49.89.289.28323
Gebäude: N1 (Theresienstr. 90)
Raum: N2114
Email: o.lenke@tum.de
Lebenslauf
- Seit 2020 Doktorand am LIS
- 2018-2020 Werkstudent am LIS
- 2018-2020 Master EI (TUM)
- 2015-2018 Bachelor EI (TUM)
- 2016-2019 Tutor für u.a. Werkstoffe der Elektrotechnik, Regelungssysteme, ...
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Angebotene Arbeiten
Laufende Arbeiten
Generischer AXI-Traffic-Analyser zur Charakterisierung von Speicher- und Buszugriffen in eingebetteten Systemen
Beschreibung
Ziel dieser Bachelorarbeit ist die Konzeption und prototypische Umsetzung eines generischen AXI-Traffic-Analysers, der an beliebigen Stellen eines Systems mit AXI-Interface instanziiert werden kann. Der Analyser soll es ermöglichen, den Datenverkehr auf dem Bus flexibel an unterschiedlichen Beobachtungspunkten zu erfassen und auszuwerten. Damit soll eine wiederverwendbare Hardware-Komponente entstehen, die zur Charakterisierung von Kommunikations- und Speicherzugriffsmustern eingesetzt werden kann.
Neben klassischen Kenngrößen wie Datenrate, Zugriffsrate oder Verhältnis von Lese- und Schreibzugriffen sollen insbesondere weiterführende Metriken zur Beschreibung des Zugriffsverhaltens untersucht und implementiert werden. Dazu gehören unter anderem die Verteilung von Strides zwischen aufeinanderfolgenden Speicherzugriffen, die Stabilität dieser Strides über die Zeit, die Dominanz bzw. Verteilung einzelner Cores oder Initiatoren auf dem Bus sowie die Abschätzung des aktuellen Working Sets, beispielsweise über die Anzahl gleichzeitig genutzter Speicherseiten. Darüber hinaus soll analysiert werden, ob ein beobachtetes System eher konstantes oder stark schwankendes Zugriffsverhalten aufweist.
Der AXI-Traffic-Analyser soll zunächst so ausgelegt werden, dass seine Messdaten über den Bus ausgelesen werden können. Bereits bei der Architektur und Schnittstellendefinition soll jedoch eine spätere Erweiterung hin zu einer non-intrusiven Ethernet-Streaming-Variante berücksichtigt werden. Perspektivisch soll der Analysator somit nicht nur lokal auslesbare Statistiken bereitstellen, sondern auch eine kontinuierliche Übertragung von Messdaten über Ethernet unterstützen, sobald ein entsprechendes Interface im Gesamtsystem verfügbar ist.
Im Rahmen der Arbeit sollen die Anforderungen an einen solchen Analysator definiert, eine Hardware-Architektur entworfen und ein erster Prototyp implementiert sowie beispielhaft evaluiert werden.
Voraussetzungen
- Good Knowledge about MPSoCs
- Good C programming skills
- Very good VHDL programming skills
- High motivation
- Self-responsible workstyle
Kontakt
Oliver Lenke
o.lenke@tum.de
Betreuer:
Evaluation of a Page-Based Memory Preload Architecture Using Standardized Embedded Benchmarks
Beschreibung
Modern MPSoC architectures are increasingly limited by off-chip memory latency. To mitigate this bottleneck, a page-based hardware preload unit has been developed that speculatively transfers DRAM pages upon last-level cache misses in order to hide memory access latency.
The goal of this bachelor thesis is to perform a systematic and scientifically sound evaluation of this architecture using internationally recognized embedded benchmark suites. The work will focus on identifying, porting, and executing suitable bare-metal benchmarks on an FPGA-based RISC-V platform (CVA6 architecture). Candidate benchmark suites include Embench, CoreMark, PolyBench/C, MiBench, and other memory-intensive workloads. The final selection will be made during the course of the thesis based on feasibility and relevance.
The thesis involves implementing the benchmarks in the existing hardware/software framework, conducting structured performance measurements, and comparing different system configurations (e.g., with and without the preload unit). Particular emphasis will be placed on analyzing memory behavior, working-set characteristics, and access patterns.
Beyond implementation, the thesis will provide a scientific evaluation of how different workload classes interact with page-based preloading. Results will be analyzed quantitatively and presented in a clear and reproducible manner using normalized speedups and workload classifications.
The outcome of this work will provide a solid experimental foundation for further research and potential publications in the area of memory-optimized MPSoC architectures.
Voraussetzungen
- Good Knowledge about MPSoCs
- Good C programming skills
- Basic understanding of hardware-oriented programming style
- High motivation
- Self-responsible workstyle
Kontakt
Oliver Lenke
o.lenke@tum.de
Betreuer:
Student
Balancing Preload Efficiency and Responsiveness through Adaptive Burst Lengths
Beschreibung
Page-based memory preloading typically relies on fixed burst lengths to transfer data efficiently from DRAM. While long bursts maximize preload throughput, they reduce responsiveness to demand-driven CPU memory accesses. Short bursts improve reactivity but underutilize available memory bandwidth.
This thesis builds on the existing page-based preload unit and investigates a hardware-based mechanism for dynamically adjusting preload burst length according to current memory system utilization. The goal is to balance preload efficiency and fast reaction to demand accesses at runtime. The proposed mechanism adapts burst length based on simple runtime indicators such as DRAM activity or the presence of competing CPU requests. The implementation extends the existing preload FSM and does not require any modifications to the CPU microarchitecture
Evaluation on an FPGA-based platform analyzes execution time, interference with demand accesses, and bandwidth utilization under different memory-intensive workloads. The results aim to demonstrate that adaptive burst sizing is an effective and low-overhead technique to improve the robustness of memory-side preloading.
Voraussetzungen
- Good Knowledge about MPSoCs
- Good C programming skills
- High motivation
- Self-responsible workstyle
Kontakt
Oliver Lenke
o.lenke@tum.de
Betreuer:
Student
Abgeschlossene Arbeiten
Integration of a Hardware Preload Unit into an AXI-based CVA6 Architecture
Working Student Job, Robert Zamora, April 2026
A Tightly LLC-Coupled Spatial-Locality- and History-Aware Memory Preload Unit
Master's Thesis, Martin Münch, March 2026
Development of a Hardware Test Framework for Simulation and FPGA-Based Evaluation
Bachelor's Thesis, Penelope Duntze, March 2026
FPGA-Based Design and Implementation of Dynamic Preloading Features
Bachelor's Thesis, Kateryna Liudkevich, Feburary 2026
Non-Intrusive Performance Monitoring Framework for a Memory Preloading Module
Master's Thesis, Aleksa Stojkovic, December 2025
Design and Implementation of Dynamic Preloading Features on an FPGA Prototype
Bachelor's Thesis, Theodor Ettling, October 2025
Evaluation Framework for a SystemC-based MPSoC Prototype Architecture
Working Student Job, Mateus Lima, September 2025
Design and Integration of a Hardware Performance Counter Unit for Memory Access Statistics
Bachelor's Thesis, Matteo Calabrò, August 2025
Design of a Prioritization Logic for a Page Preloading Mechanism
Research Practice, Jakob Winterer, July 2025
Integration of a Hardware Preload Unit into an AXI-based CVA6 Architecture
Bachelor's Thesis, Robert Zamora, June 2025
Exploring Optimal Memory Transfer Schedules in Hierarchical Memory Architectures: A Benchmark Study on the Streaming Transfer Controller of the TC4x PPU for Embedded AI Workloads
Master's Thesis, Radhika Rajeev Nair, April 2025, Cooperation with Infineon AG
Analysis and Visualization of Cache Access Behavior in CPU Clusters
Bachelor's Thesis, Klimentij Batenko, March 2025
Analyse von Laufzeit-Statistiken eines SystemCMPSoC-Simulationsmodells mit Python
Bachelor's Thesis, Quynh Thy Laura Vo, March 2025
Evaluation Framework for a SystemC-based MPSoC Prototype Architecture
Bachelor's Thesis, Mateus Lima, Feburary 2025
Memory Access Prioritisation on an FPGA-Based MP-SoC System
Research Practice, Jonathan Ross, Feburary 2025
Development of a C Testsuite for a Memory Preloading Mechanism of an MPSoC
Bachelor's Thesis, Fabian Strasser, December 2024
Fine granular Page Preloading Mechanism on an FPGA Prototype
Research Practice, Aurel Prestel, November 2024
Investigating DMA Transfer Configurations for Optimal Utilization of DDR Memory Bandwidth
Research Practice, Seçkin Gezer, October 2024, Cooperation with WORK Microwave
Design and Implementation of a Stride Prefetching Mechanism in SystemC
Research Practice, Sruthi Haridas, July 2024
Design and Implementation of a Memory Prefetching Mechanism on an FPGA Prototype
Master's Thesis, Christoph Foltyn, June 2024
Interrupt Latency Investigations with YoctoRT and FreeRTOS on Xilinx Versal Evaluation Board
Master's Thesis, Kiran Bhandarkar, April 2024, Cooperation with Rohde&Schwarz
SystemC Model for Memory Preloading
Research Practice, Ali Emre Heybeli, February 2024
An Efficient, Scalable and SIMD-friendly Hybrid FFT Computation Method
Master's Thesis, Jiawen Qi, January 2024, Cooperation with Huawei
SystemC Model for Memory Preloading
Research Practice, Jingyi Liu, December 2023
Lifetime Analysis of Flash Memory Devices in Automotive Use Cases
Bachelor's Thesis, Simon Weigl, July 2023, Cooperation with BMW AG
Automatic Hardening of Registers in Safety Critical Microcontrollers
Bachelor's Thesis, Jonathan Ross, July 2023, Cooperation with Infineon AG
Design and Implementation of a flexible SPI Fault Injection Unit
Bachelor's Thesis, Hannes Matheis, December 2022, Cooperation with Infineon AG
Design and Implementation of a Hardware Accelerator for VSM Page Writeback
Master's Thesis, Thomas Leyk, November 2022, Cooperation with FAU
Scalability Analysis of Hardware Acceleration on Central and Distributed Memory Systems
Master's Thesis, Jens Nöpel, November 2022
Measurement and Analysis of a Tile-based MPSoC System
Research Practice, Gabriel Pempel, November 2022, Cooperation with FAU
Design and Implementation of a HW-based Memory Protection Unit for Tile-based MPSoCs
Master's Thesis, Peter Körner, October 2022, Cooperation with FAU
DYNAMIT: Dynamic Acceleration of Memory-Stores in Tile-based Architectures
Master's Thesis, Michael Geier, August 2022
Laufzeit Vorhersage von Hardwarebeschleuniger und Near-Memory-Computing
Bachelor's Thesis, Sahil Salotra, September 2021
Extending an Utilization Counter Framework for On-Chip AHB Bus Systems
Bachelor's Thesis, Humayra Jeba Binte Mohd Habibur Rahman, July 2021, Cooperation with SIT
Best Thesis Award
Utilization Monitoring and Analysis of a Near-Memory-Computing System
Research Practice, Richard Petri, May 2021
Publikationen
2025
2024
2023
- Information Processing Factory 2.0 - Self-awareness for Autonomous Collaborative Systems. DATE 2023, 2023 mehr… BibTeX Volltext ( DOI )
2022
- Invasive NoCs and Memory Hierarchies for Run-Time Adaptive MPSoCs. In: Invasive Computing. FAU University Press, Universitätsstraße 4, 91054 Erlangen, 2022 mehr… BibTeX Volltext ( DOI )
- Validation and Demonstrator. In: Invasive Computing. FAU University Press, Universitätsstraße 4, 91054 Erlangen, 2022 mehr… BibTeX
2021
2020
- X-CEL: A Method to Estimate Near-Memory Acceleration Potential in Tile-based MPSoCs. ARCS 2020 - 33rd International Conference on Architecture of Computing Systems, 2020 mehr… BibTeX
- DySHARQ: Dynamic Software-Defined Hardware-Managed Queues for Tile-Based Architectures. International Journal of Parallel Programming, 2020 mehr… BibTeX Volltext ( DOI )
- X-Centric: A Survey on Compute-, Memory- and Application-Centric Computer Architectures. MEMSYS'20: The International Symposium on Memory Systems , 2020 mehr… BibTeX