• Scalability
• Compelxity
• Servicability

In the context of rapid advancements in intelligent transportation and autonomous driving technologies, Anomaly Detection in Video/Sequential Images has emerged as a core technology for ensuring driving safety and enhancing system robustness. Unlike traditional static image recognition, vehicles operate in a highly dynamic, complex, and unpredictable three-dimensional world. Therefore, the ability to process continuous visual information in real-time and identify "unusual" events is crucial for intelligent vehicles.

Here, we aim to investigate which algorithms are best suited to the application and what advantages and disadvantages they offer. 

With diminishing performance gains from node shrinking in recent years, hardware manufacturers have been gravitating towards architectural improvements to squeeze more performance out of hardware. This shift has pushed the industry increasingly towards heterogeneous multi-core systems. Prominent examples of this are Big.LITTLE cores on ARM CPUs [1] and P-cores and E-cores on Intel CPUs [2]: two types of CPU cores used on the same chip to balance performance and power efficiency. This trend extends beyond the use of multiple core types to include on-chip hardware accelerators.

Resource allocation refers to the assignment of a task to a specific hardware resource (e.g., a CPU core or an Accelerator). A naive approach to perform resource allocation would be to statically assign each task to a specific resource at design time. This, however, can quickly lead to over-provisioning and, consequently, low resource utilization. Also, task execution time can fluctuate vastly depending on the input data. Consequently, dynamic resource allocation, in which task/resource mappings are determined at runtime, is explored as an alternative to static allocation. This is a difficult problem to solve, especially considering the hybrid nature of heterogeneous systems.

In this seminar work, we want to survey the literature for different approaches to the dynamic resource allocation problem in heterogeneous multicore systems using Reinforcement Learning (RL). RL has proven to be a solid choice for solving similar problems where the environment dynamics are either stochastic or too complex to model . There are multiple directions this work can take, such as DAG-based, model-free, and energy-aware methods. The student is free to pursue the work as they please within the pre-defined scope in the description.

Here are a couple of papers as a starting point. These are just examples. The student is free to include any papers they deem fit the topic in their work:

• Grinsztajn, N., Beaumont, O., Jeannot, E., & Preux, P. (2021, September). Readys: A reinforcement learning based strategy for heterogeneous dynamic scheduling. In 2021 IEEE International Conference on Cluster Computing (CLUSTER) (pp. 70-81). IEEE.

• Liu, Y., & Wu, J. (2025, October). Dynamic Scheduling in Heterogeneous Non-Preemptive Pipeline Systems: A Reinforcement Learning Approach. In 2025 5th International Conference on Electronic Information Engineering and Computer Technology (EIECT) (pp. 480-484). IEEE.

• Lin, Z., Li, C., Tian, L., & Zhang, B. (2022). A scheduling algorithm based on reinforcement learning for heterogeneous environments. Applied Soft Computing, 130, 109707.

• Mao, H., Schwarzkopf, M., Venkatakrishnan, S. B., Meng, Z., & Alizadeh, M. (2019). Learning scheduling algorithms for data processing clusters. In Proceedings of the ACM special interest group on data communication (pp. 270-288).

References:

[1] https://www.arm.com/technologies/big-little

[2] https://www.intel.com/content/www/us/en/gaming/resources/how-hybrid-design-works.html

Modern I/O devices and accelerators increasingly rely on virtual memory support in order to simplify programming, improve isolation, and enable shared virtual address spaces with CPUs. However, address translation on the device side is often expensive. When an IOMMU or device TLB misses, the accelerator may suffer significant stalls due to multi-level page table walks and limited translation locality. Prior work has shown that translation overhead can become a major bottleneck for accelerators and that hiding or restructuring translation latency is an important architectural problem.

At the same time, traditional prefetching research mainly focuses on data accesses, while the translation path itself can also be seen as a target for latency hiding. This raises an interesting question: instead of only prefetching data, can we also prefetch translation-related information, such as page-table entries, or redesign the translation path so that address translation and data access can overlap more effectively? Recent and prior studies suggest that this direction is promising for accelerator-centric systems.

The goal of this seminar is to build a clear architectural understanding of how prefetching and address translation can be combined for accelerators or IO systems. The seminar will compare different approaches, identify their main design trade-offs, and discuss whether translation-path prefetching could become an important design direction for future heterogeneous systems

Prerequisites

Large language model(LLM) inference is increasingly limited by memory access rather than pure computation, especially in long-context and decoding scenarios. A major reason is the high cost of moving model weights and KV cache data across the memory hierarchy. Recent work shows that prefetching can be used to overlap memory movement with ongoing computation or communication.

Compared with traditional hardware prefetching, LLM inference introduces a different setting. The prefetched object is no longer a small cacheline but larger units such as KV blocks. Moreover, prefetch timing depends on token generation, layer execution order, and runtime scheduling. Some recent studies also suggest that temporal patterns in attention behavior can be exploited to guide KV cache management and cross-token prefetching more effectively.

The goal of this seminar is to build a clear understanding of how prefetching concepts can be extended to AI inference systems. The student will compare recent approaches for KV cache and weight prefetching, discuss and summarize their architectural trade-offs, and determine whether LLM-serving workloads require new prefetching principles beyond those in CPU memory  hierarchies

Prerequisites

This seminar will examine software-based Control-Flow Integrity (CFI) methods, focusing on techniques such as static analysis, compiler instrumentation, and runtime checks to enforce control-flow security at the program level. It will evaluate their advantages, including wide applicability and easier integration with existing systems, as well as limitations such as higher runtime overhead and potential precision issues. The seminar will also briefly compare these approaches with hardware-based CFI methods, emphasizing trade-offs between performance, security guarantees, and deployment complexity.

This seminar will explore hardware-based Control-Flow Integrity (CFI) methods, focusing on techniques such as shadow stacks, branch monitoring, and specialized instructions to enforce control-flow security at the processor level. It will analyze their benefits, including strong security guarantees and low runtime overhead, as well as drawbacks like hardware complexity and limited compatibility with legacy systems. The seminar will also briefly compare these methods with software-based CFI approaches, highlighting trade-offs such as flexibility versus performance and ease of deployment.

As automotive architectures transition from legacy bus systems to high-speed Automotive Ethernet, the Audio Video Transport Protocol (AVTP) has become the standard for transporting time-sensitive data, including ADAS camera feeds, infotainment streams, and critical control traffic. However, this transition opens new attack vectors: an adversary could inject malicious frames to freeze a backup camera or spoof control messages within the AVTP stream, potentially leading to catastrophic failures.

This seminar focuses on the unique challenges and methodologies for implementing Intrusion Detection Systems (IDS) within the IEEE 1722 framework. 

Efficient use of the available computing resources is an important to achieve the best possible performance of a computing platform. A key component in such architectures is the operating system, which provides an interface for other software and application to run and use the hardware.

As many applications can run concurrently and therefor compete for the available compute resources, the operating system is responsible for providing the desired scheduling. While this has been historically the job of the kernel, numerous approaches exist to move some functionality of task and thread scheduling into user space.

This seminar topic should analyze the different approaches for userspace scheduling, highlighting their differences by looking at their implementation, performance, and motivation.

In today’s data-driven world, processing approaches are typically divided between cloud-based solutions—with virtually unlimited resources—and localized processing, which is constrained by hardware limitations. While the cloud offers extensive computational power, localized processing is often required for real-time applications where latency and data security are critical concerns.

To bridge this gap, various algorithms have been developed to pre-process data or extract essential information before it is sent to the cloud.

The goal of this seminar is to explore and compare these algorithms, evaluating their computational load on local hardware and their overall impact on system performance.

Embedded FPGA (eFPGA) [1] is an FPGA fabric integrated into another chip, usually a System-on-Chip (SoC). The FPGA fabric can be programmed to perform arbitrary computation, generally acting as a programmable, flexible hardware accelerator. 

 eFPGAs have attracted attention in recent years due to their higher computational density compared to CPU cores, especially as Dennard scaling slows. Traditionally, companies used proprietary, closed-source FPGA fabric designs and the tools used to create them, severely limiting their adoption. However, over the last few years, some open-source alternatives have been proposed. These solutions offer a full pipeline from specification to netlist. This allows HW designers to easily integrate eFPGAs into their designs, significantly reducing the design effort. 

In this work, the student is tasked with investigating these open-source eFPGA design frameworks. The main goal is to compare these frameworks and highlight their key differentiators. 

Below is a list of papers presenting such frameworks. These are not necessarily the ones that will be included in the final deliverable. The student is free to include any papers they deem fit the topic in their work: 

• Tang, X., Giacomin, E., Alacchi, A., Chauviere, B., & Gaillardon, P. E. (2019, September). OpenFPGA: An opensource framework enabling rapid prototyping of customizable FPGAs. In 2019 29th International Conference on Field Programmable Logic and Applications (FPL) (pp. 367-374). IEEE. 
• Koch, D., Dao, N., Healy, B., Yu, J., & Attwood, A. (2021, February). FABulous: An embedded FPGA framework. In The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (pp. 45-56). 
• Li, A., & Wentzlaff, D. (2021, February). PRGA: An open-source FPGA research and prototyping framework. In The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (pp. 127-137). 

References: 

[1] https://anysilicon.com/efpga/ 

As network speeds continue to outpace CPU performance, traditional host-based network stack processing becomes a critical bottleneck in modern systems. SmartNICs, with their programmable processing capabilities, enable offloading network stack functionality from the host to the network interface, potentially improving performance and resource efficiency.

This seminar explores recent approaches to network stack offloading on SmartNICs, focusing on different architectural design strategies. These include approaches that aim to transparently offload existing transport protocols (e.g., TCP) to the SmartNIC, as well as designs that rethink and restructure the network stack around SmartNIC-centric execution.

Key aspects to investigate include performance characteristics, CPU and memory utilization, programmability, and deployment complexity. The goal is to analyze the trade-offs between transparency, flexibility, and efficiency, and to assess how different design choices influence system behavior in high-performance networked environments.

As systems-on-chip continue to grow in complexity and chiplet-based architectures increasingly split functionality across multiple dies, the amount of data that must be transferred between system components continues to rise. While this can be addressed by increasing interconnect bandwidth and lane count, area, power consumption, and pin requirements also increase.

One way to reduce the load on such bandwidth-constrained links is to compress data on-the-fly before transmission. In this context, low latency and high throughput are more critical than high compression ratios, and lossless compression algorithms from the Lempel-Ziv family are especially interesting for their generally favorable trade-off between compression efficiency and implementation cost.

In this seminar work, the student should investigate hardware implementations of lossless data compression algorithms, with a focus on the Lempel-Ziv family, such as LZ4. The goal is to compare different architectural concepts and implementation choices with respect to throughput, latency, maximum frequency, and resource usage. In particular, the student should examine which algorithmic properties make an approach more or less suitable for hardware realization, such as the degree of inherent parallelism, the complexity of match search and reference generation, or the handling of variable-length coding and control flow. For dictionary-based methods, aspects such as efficient lookup mechanisms, for example, hash-based indexing or other compact search structures, are especially relevant. In addition, the student should assess how well these approaches fit a pin-constrained chiplet interconnect with strict latency requirements, and discuss which algorithmic or architectural decisions are most promising for such a target system.

Potential starting points for literature research could be the following papers:
https://arxiv.org/html/2409.12433v1
https://dl.acm.org/doi/abs/10.1145/3542637.3543701
https://dl.acm.org/doi/10.1145/3316551.3316564
https://ieeexplore.ieee.org/abstract/document/8306366
https://dl.acm.org/doi/abs/10.1145/2664666.2664670
https://ieeexplore.ieee.org/abstract/document/7160039

???????????????????????????????????????????????????????????????????????????? ????????????????????????????????????????

??????????????????????????????????????????????????????????????????

• ????????
  ????????????????????????
• ??????????
  ???????????????????????????????????
• ???????????
  ????????????????????????????????????
• ?????????
  ??“???????”?????????

?????????????????????????????????????????????????????????????????????????