Mannheim EMDRIVE is a BMBF-funded project for the conception and realtime(RT)-compatible extension of central computing platforms and embedded compute networks for future highly automated vehicles. The project network consists of several industry partners from the automotive industry accompanied by partners from academia.
The overall goal of the partners in the course of the project is the development of a hierarchical, scalable platform concept for centralized high performance automotive RT-compute boardnets (Sensor2Edge) and the transfer of results to automotive industry. This can be broken down into the following subgoals within the project:
Embedded RT Compute Performance
Power Consumption
Dynamic, Distributed Computing
RT-Monitoring and Diagnosis
Our Contribution: RT Monitoring and Diagnosis
Modern vehicles already host 100+ Electronic Control Units (ECUs) running more than 100 million lines of code—and software complexity will only grow with autonomous-driving features. Because many sporadic, software-induced faults escape lab testing, vehicles need an in-field mechanism to observe, diagnose, and adapt throughout their lifetime.
Our solution, the Diagnosis Unit (DU), delivers exactly that. Built as a modular HW/SW co-design that can be retro-fitted at a gateway’s mirror port, the DU provides cross-layer, real-time monitoring while remaining virtually invisible to normal in-vehicle operation.
How It Works
Ethernet-Traffic Snooping
The DU taps mirrored traffic on the zonal gateway and applies threshold- and ML-based analytics to detect anomalies such as timing irregularities, message-injection patterns, or traffic-burst deviations.
Microcontroller Trace Analysis
When a network anomaly is flagged, the DU remotely configures the target ECU’s Multi-Core Debug Solution (MCDS) via TAS, records a short execution trace, and analyzes CPU load, control-flow deviations, and timing violations.
Dynamic Anomaly Tree (DAT)
A runtime-reconfigurable tree links communication symptoms to likely processing-level root causes. The backend can update this tree on-the-fly across an entire fleet, turning every car into a collaborative diagnostics sensor.
Edge-to-Cloud Workflow
Heavy data (raw traces) is processed locally on a Zynq UltraScale+ ZCU102 platform (PL for packet parsing, PS for analysis). Only compact summaries—typically a few kB—are uploaded for fleet-wide orchestration and expert review, minimizing bandwidth overhead.
Why It Matters
Reconfigurable & Future-Proof – Cloud-driven updates let the DU adapt to new fault patterns without workshop visits.
Minimal Intrusion – Operates on mirrored Ethernet traffic; no extra latency or bandwidth impact on the IVN.
Comprehensive Coverage – Correlates system-level network symptoms with component-level execution traces, enabling root-cause insight instead of mere symptom reporting.
With its flexible architecture and fleet-coordinated intelligence, the Diagnosis Unit pushes automotive runtime monitoring beyond static OBD routines—empowering engineers to uncover and fix elusive, software-driven faults long after vehicles leave the factory floor.
Current work
Simulation of Zonal In-Vehicle Network Architectures Ongoing development and evaluation of Ethernet-based zonal IVNs using OMNeT++, modeling Time-Sensitive Networking (TSN) behavior and ECU communication flows across mirrored gateway ports.
AI-Based Ethernet Anomaly Detection Implementation of anomaly detection mechanisms using deep learning models such as LSTM autoencoders and Transformer architectures in Python (TensorFlow/Keras). These models aim to identify timing irregularities, unexpected traffic bursts, and ID sequence anomalies in live Ethernet traffic.
AUTOSAR Integration on Infineon AURIX (TC397) Development of diagnostic and control logic on Infineon AURIX TC397 microcontrollers, including AUTOSAR-compliant applications responsible for real-time vehicle sub-functionality (e.g., lane detection, control logic, actuation).
Real-Time Microcontroller Trace Collection via MCDS Leveraging the Multi-Core Debug Solution (MCDS) integrated in the AURIX TC397 to collect fine-grained execution traces. These traces are triggered and retrieved via the Tool Access Socket (TAS) server interface, and subsequently analyzed to detect processing anomalies such as excessive instruction duration, memory misaccesses, or execution flow deviations.
Trace Analysis and Cloud-Coordinated Diagnosis Development of a modular Trace Analyzer hosted on the Zynq UltraScale+ MPSoC, capable of identifying anomalous runtime behavior through timing and control-flow analysis. Diagnostic results are compiled into compact summaries and sent to a centralized cloud backend, which maintains a Dynamic Anomaly Tree (DAT) and orchestrates fleet-wide diagnosis strategies through over-the-air reconfiguration.
Categorization of Ethernet-Detected Anomalies Induced by Processing Unit Deviations
Description
Sporadic anomalies in automotive systems can degrade performance over time and may originate from various system components. In automotive applications, anomalies are often observed at the sensor and ECU levels, with potential propagation through the in-vehicle network via Ethernet. Such anomalies may be the result of deviations in electronic control units, highlighting the importance of monitoring these signals over Ethernet.
Not all processing anomalies are equally detectable over Ethernet due to inherent limitations in the monitoring techniques and the nature of the anomalies. This seminar will explore various anomaly categories, investigate their potential causes, and assess the likelihood of their propagation through the network.
The goal of this seminar is to provide a comprehensive analysis of these anomaly categories, evaluate the underlying causes, and discuss the potential for their detection and mitigation when monitored over Ethernet.
Localizing Automotive Diagnostic Solutions: Software Migration and PS/PL Interface Implementation on ZCU102
Description
About the Project: Future cars rely on a wide variety of sensors—including cameras, LiDARs, and RADARs—that generate enormous amounts of data. This data flows through the intra-vehicular network (IVN) to processing nodes, ultimately triggering actuators. With strict timing constraints essential for vehicle safety, time-sensitive networking (TSN) is now a critical component in modern automotive systems. Within the context of the EMDRIVE project, our team is developing new monitoring and diagnostic approaches to detect errors early and maintain functional safety in highly automated driving environments.
Project Description: The primary goal of this project is to migrate existing software packages—used to record ECU traces and analyze processing anomalies—onto the ZCU102 board. This migration will enable local processing of anomalies and establish a robust PS/PL interface between the anomaly detection hardware (implemented on the FPGA) and the processing system running the software.
The key tasks include:
TAS Tool Configuration: Bring up the TAS tool and configure it to work with the Multi Core Debug Solution (MCDS) for trace recording.
Trace Analyzer Deployment: Bring up and configure the Trace Analyzer to parse recorded traces and detect deviations in processing.
Software Migration: Migrate the existing software packages to run on the Processing System (PS) of the ZCU102 board.
Interface Integration: Develop and integrate a stable interface between the Programmable Logic (PL) and the PS, ensuring efficient sharing of data, status, and configuration information.
Key Responsibilities:
Analyze existing software packages and understand the hardware integration requirements.
Configure and validate both the TAS tool and the Trace Analyzer.
Adapt and optimize software for deployment on the ZCU102 board.
Develop and implement a robust PS/PL interface for seamless communication between hardware and software.
Collaborate with interdisciplinary teams to integrate and test the complete system.
Prerequisites
Required Skills:
Proficiency in C programming.
Strong understanding of System-on-Chip (SoC) architectures and microcontroller modules.
Background in automotive applications and systems.
Experience with hardware description languages (e.g., VHDL) and embedded systems (preferred).
Familiarity with Linux-based systems and FPGA integration is a plus.
Benefits:
Hands-on experience with cutting-edge automotive diagnostic technology.
Exposure to advanced hardware-software integration and embedded systems.
Opportunity to contribute to projects that enhance the safety and reliability of future vehicles.
Collaborative work environment with industry-leading partners.
Analysis Algorithms for Processor Traces and Instructions
Description
Modern CPUs execute a vast number of instructions while managing large volumes of data. On-chip debugging modules, located adjacent to the CPU, play a critical role in capturing valuable execution information. This data is essential for analyzing system behavior and detecting anomalies—such as timing issues or execution faults—that may occur in the processing unit.
Over time, various algorithms have been developed to analyze processor traces and instructions. These algorithms not only deepen our understanding of system behavior but also support the debugging of potential faults and anomalies.
The goal of this seminar is to explore and compare different trace analysis algorithms, and that is by evaluating their efficiency, performance, and potential applications in debugging and optimizing processor operations.
Contact
Zafer Attal
zafer.attal@tum.de
Supervisor:
Zafer Attal
Open Work
If you are interested in any of the current work items that are mentioned above and there is currently no open position, please do not hesitate to contact Zafer Attal.
Completed Work
Non-Intrusive Monitoring of Core Utilization on a Multicore Automotive Control Unit (Master Thesis, 2023)
Simulation of Zonal-Architecture Intra-Vehicular Network with TSN Functionality (Teaching Assistant, 2022–2023)
Implementation of a Real-Time Diagnosis Unit Prototype on ZCU102 Designed and implemented a hardware/software co-design on a Zynq UltraScale+ MPSoC (ZCU102), splitting diagnostic tasks between the Programmable Logic (PL) for Ethernet packet parsing and the Processing System (PS) for trace analysis and backend communication.
Integration of Anomaly Detection in Ethernet Traffic Configured the DU to detect specific Ethernet anomalies such as timing deviations, burst inconsistencies, and traffic pattern changes, using empirical thresholds and real traffic profiles.
Aurix ECU Trace Triggering and Retrieval via TAS Connected the DU to Infineon Aurix TC397 boards using TAS to remotely configure, trigger, and retrieve execution traces via the Multi-Core Debug Solution (MCDS).
Demonstration Setup and Validation in a Simulated Function Chain Implemented a testbed with three Aurix boards simulating a Lane Keeping Assistant (LKA). Successfully validated end-to-end detection of communication anomalies, triggering of trace capture, and analysis of processing deviations.
Patrick Schmidt, Iuliia Topko, Matthias Stammler, Tanja Harbaum, Juergen Becker, Rico Berner, Omar Ahmed, Jakub Jagielski, Thomas Seidler, Markus Abel, Marius Kreutzer, Maximilian Kirschner, Victor Pazmino, Robin Sehm, Lukas Groth, Andrija Neskovic, Rolf Meyer, Saleh Mulhem, Mladen Berekovic, Matthias Probst, Manuel Brosch, Georg Sigl, Thomas Wild, Matthias Ernst, Andreas Herkersdorf, Florian Aigner, Stefan Hommes, Sebastian Lauer, Maximilian Seidler, Thomas Raste, Gasper Bozic, Ibai Irigoyen Ceberio, Muhammad Hassan, Albrecht Mayer: EMDRIVE Architecture: Embedded Computing And Diagnostics From Sensor To Edge. DATE 2024 - Design, Automation and Test in Europe Conference, 2024 more…
Gasper Skvarc Bozic, Ibai Irigoyen Ceberio, Matthias Ernst, Albrecht Mayer: A New Generation Automotive Tool Access Architecture for Remote in-Field Diagnosis. WCX SAE World Congress Experience 2023, 2023 more…
