Open Theses

Background

With the rapid development of Cloud in the recent years, attempts have been made to bridge the widening gap between the escalating demands for complex simulations to be performed against tight deadlines and the constraints of a static HPC infrastructure by working on a Hybrid Infrastructure which consists of both the current HPC Clusters and the seemingly infinite resources of Cloud. Cloud is flexible and elastic and can be scaled as per requirements.

The BMW Group, which runs thousands of compute-intensive CAEx (Computer Aided Engineering) simulations every day needs to leverage the various offerings of Cloud along with optimal utilization of its current HPC Clusters to meet the dynamic market demands. As such, research is being carried out to schedule moldable CAE workflows in a Hybrid setup to find optimal solutions for different objectives against various constraints.

Goals

1. The aim of this work is to develop and implement scheduling algorithms for CAE workflows on a Hybrid Cloud on an existing simulator using meta-heuristic approaches such as Ant Colony or Particle Swarm Optimization. These algorithms need to be compared against other baseline algorithms, some of which have already been implemented in the non-meta-heuristic space.
2. The scheduling algorithms should be a based on multi-objective optimization methods and be able to handle multiple objectives against strict constraints.
3. The effects of moldability of workflows with regards to the type and number of resource requirements and the extent of moldability of a workflow is to be studied and analyzed to find optimal solutions in the solution space.
4. Various Cloud offerings should be studied, and the scheduling algorithms should take into account these different billing and infrastructure models while make decisions regarding resource provisioning and scheduling.

Requirements

• Experience or knowledge in Scheduling algorithms
• Experience or knowledge in the principles of Cloud Computing
• Knowledge or Interest in heuristic and meta-heuristic approaches
• Knowledge on algorithmic analysis
• Good knowledge of Python

We offer:

•   Collaboration with BMW and its researchers
•   Work with industry partners and giants of Cloud Computing such as AWS
•   Solve tangible industry-specific problems
•  Opportunity to publish a paper with your name on it

What we expect from you:

• Devotion and persistence (= full-time thesis)
• Critical thinking and initiativeness
• Attendance of feedback discussions on the progress of your thesis

The work is a collaboration between TUM and BMW

Apply now by submitting your CV and grade report to Srishti Dasgupta (srishti.dasgupta(at)bmw.de)

Background: Social good applications such as monitoring environments require several technologies, including federated learning. Implementing federated learning expects a robust balance between communication and computation costs involved in the hidden layers. It is always a challenge to diligently identify the optimal values for such learning architectures. 

Keywords: Edge, Federated Learning, Optimization, Social Good,  

Research Questions: 

1.     How to design a decentralized federated learning framework that applies to social good applications?

2.     Which optimization parameters need to be considered for efficiently targeting the issue?

3.     Are there any optimization algorithms that could deliver a tradeoff between the communication and computation parameters?

Goals: The major goals of the proposed research are given below: 

1.     To develop a framework that delivers a decentralized federated learning platform for social good applications.   

2.     To develop at least one optimization strategy that addresses the existing tradeoffs in hidden neural network layers. 

3.     To compare the efficiency of the algorithms with respect to the identified optimization parameters.  

Expectations: The students are expected to have an interest to develop frameworks with more emphasis on federated learning; they have to committedly work and participate in the upcoming discussions/feedbacks (mostly online); they have to stick to the deadlines which will be specified in the meetings. 

For more information, contact: Prof. Michael Gerndt (gerndt@tum.de) and Shajulin Benedict (shajulin@iiitkottayam.ac.in)

Background:

The Flux scheduler is a graph-based hierarchical scheduler for exascale systems that has been developed by the Lawrence Livermore Nation Laboratory to schedule HPC workloads with an efficient temporal management scheme across a range of HPC resources. Since it is graph-based, resource scheduling can be broken down to different levels. The flux scheduler has been extended to run on the Cloud as well and is flexible and elastic in its design.

Workflows represent a set of inter-dependent steps to achieve a particular goal. For example, a machine learning workflow is a series of steps for developing, training, validating and deploying machine learning models. In particular, a LLM(Large Language Model) workflow includes additional steps that define the complexities for training and deploying language models. These workflows are iterative in nature and each stage may inform changes in previous steps as the model’s limitations and new requirements emerge. Accordingly, the computational requirements vary and the hierarchical scheduler should adapt accordingly for each splitted data set by the resources (Cloud+HPC) growing and shrinking to reduce costs, deadlines and avail optimal resource utilization.

The work would be a part of the new field of Computer Science, namely Converged Computing, that aims to bridge the gap between Cloud technologies and the HPC world. 

Goals:

• Extend the flux scheduler to allow for the growing and shrinking of Hybrid resources as per the demands of the individual jobs or tasks. The communication between these levels need to be extended as per the already established protocols of Flux.
• Implement an infrastructure that takes in an input of MLOps workflows and schedules these and the individual tasks according to the resource requirements in each iterative step by growing and shrinking according to the scheduler.
• Implement a Hybrid Infrastructure for the workflows to run on, thus taking advantage of the flexibility and elasticity of Cloud.

Requirements:

• Experience or knowledge or interest in Kubernetes and related cloud computing concepts.
• Preferred knowledge on  MLOps workflows and other related topics
• Preferred experience on working with HPC systems and related libraries such as SLURM
• Knowledge on scheduling algorithms
• Basic knowledge of C++, Python, Linux Shell
• Basic Knowledge on TensorFlow or PyTorch

What we expect from you:

• Devotion and persistence(=full-time thesis)
• Critical thinking and ability to think out-of-the-box and take initiatives to explore ideas and use-cases
• Attendance of feedback discussions on the direction and progress of thesis

What we offer:

• Collaboration between a pioneering research center (Lawrence Livermore National Laboratory), a leader in the automobile industry (BMW) and the Technical University of Munich.
• Thesis in an area that is in the highest demand in the current industry; combining MLOps and infrastructure for MLOps, esp. in the Cloud.
• Supervision and collaboration from a multi-disciplinary team during the thesis.
• Opportunity to publish a paper with your name on it.

References:

1.    flux-framework/flux-sched: Fluxion Graph-based Scheduler

2.    Copy of HPC Knowledge Meeting: Converged Computing Flux Framework - Shared

The work is a collaboration between TUM, LLNL and BMW.

Apply now by submitting your CV and grade report to Srishti Dasgupta(srishti.dasgupta@bmw.de/srishti.dasgupta@tum.de)

Background and Motivation:

The ever increasing power consumption of supercomputers has been one of the major concerns in the HPC community since mid2000s. Therefore, there have been a variety of studies to measure and manage the power consumption of HPC systems from diverse perspectives since then. However to the best of our knowledge, analysis of power consumption on the level of library function call granularity hasn’t been investigated. This approach enables a different perspective into library’s and application’s power consumption and carbon emissions. As modern HPC applications use libraries heavily from communication, computation and memory operations, it is interesting to inspect power consumptions of the different function calls from these library functions as much as the whole application itself. By these measurements the characteristics of individual functions in the libraries on different architectures can be analysed and optimized.

Function interception is a common method used to place introspection points for instrumentation of applications. This method particularly useful when update in the source code is not desired or feasible to mark instrumentation points in the source code. There are two techniques that are commonly used for application interception at function call level. One is by utilizing function wrappers and dynamic linking the other is binary instrumentation to update the application binary. Both approaches have their strengths however for this project we will focus on function wrappers and dynamic linking approach.Wrapper generation paper: https://link.springer.com/chapter/10.1007/978-3-031-69577-3_8

Lastly the roofline model has been a standard way to understand rough characteristics of the architecture capabilities as well as the application performance in relation to the architecture capabilities. There are multiple different derivations of the model that enable slightly different or more detail into the architecture’s capabilities. For example, the cache aware roofline model is an extension of the standard roofline model that considers the effects of the memory hierarchy in the system on to the roofline model, hence presents a more realistic model. Similarly the roofline model of energy considers similar principles as the standard roofline model but it takes energy as performance metric of interest instead of traditional time metric. Hence, the flops per second is replaced by flops per joule and the operational intensity(flops per bytes transferred ). This model represents an upper bound for achievable energy efficiency of the system. Using these two roofline models it is possible to compare the time vs power efficiency of the library functions on each architecture.https://ieeexplore.ieee.org/document/6506838 and https://ieeexplore.ieee.org/document/6569852⁦

Research question:

Can we optimize application’s power consumption and carbon emission on different CPU architectures by profiling the power consumption of individual library function calls ? 

Can we make suggestions to the user for different stages of the application to optimize power consumption via techniques like down clocking ?

Goal:

Suggesting users certain libraries or library implementations over others depending on their power consumption characteristics when used with different applications on different architectures.

Suggesting users techniques to optimize their power consumption depending on the application phases or library calls made by the application.

Requirements:

1. Measurements must be at every library call function granularity.

2. Measurements must be statistically significant.

3. Measurements must include power consumption and carbon emission and other possibly related PAPI measurements to be able to relate power consumption to function characteristics

(FLOPS for computation function, Network utilisation for communication library functions )

4. The measurements should be interpreted to make suggestions to the user about how to optimize the applications power consumption on specific architectures.

Method:

• The instrumentation points are at every library function call. For intercepting the library function calls we use a wrapIt wrapper generator to generate the interface for tool changing and tool generation.
• Implement measurement code for carbon emission and power consumption of each function call.
• Take measurements by WrapIt interface and plot histogram and timeline of power consumption of each library function. Characterise the power relation of the application and the libraries.
• Compare the measurements to the power roofline and 

Evaluation method:

• Extracting Power Measurements:

We collect data at every library function call by using the WrapIt tools. These measurements will be at function call granularity and will report the power consumption and carbon emission of the entire runtime of the functions at each call. By analysing the measurements we can characterize the power consumption and carbon emission of library functions on different CPUs. These measurements are used to identify the energy and carbon bottleneck functions. 

• Function-granular energy and carbon analysis using an energy version of the roofline model: 

Identifying the energy and carbon sweet spots, and suggesting users how the code should be optimized. 

• Relational analysis between Cache aware roofline model and Roofline model of Energy:

Identifying the relationship between cache aware roofline model and Roofline model of Energy on function granularity.

• Extending the energy roofline in order to take some additional aspects into account, such as cache hits/misses and clock frequency. 

Evaluation/Verification and Contribution Outline:

Metrics to measure:

• Rapl power counters

Other Possible metrics to measure to relate with power consumption:

By PAPI Counters:

• Memory Bandwidth
• Flop rate
• Memory Utilization

Probable Libraries to Introspect :

• Hypre:  Linear Solver library. Potentially meaningful for flop rate, memory bandwidth, cache miss and power consumption measurements.
• Umpire: Portability layer for memory management (malloc,free etc.). Used by hypre

Probable applications:

• AMG (uses MPI,hypre and Umpire)
• Gene (real life code in Fortran has Communication, memory and computation libraries)

See also:

Power/performance modeling: https://link.springer.com/content/pdf/10.1007/978-3-030-50743-5_18.pdf

Power/performance modeling2: https://dl.acm.org/doi/pdf/10.1145/3547276.3548630

Software carbon emission estimation: https://dl.acm.org/doi/pdf/10.1145/3631295.3631396

Carbon estimation tool (WattTime): https://docs.watttime.org/

The Cerebras CS-2 wafer-scale engine (https://www.cerebras.ai) is a novel HPC system at LRZ that integrates 850.000 cores and 40GB of memory on the worlds largest chip for processing AI workloads. This system is installed and operated at LRZ.

This thesis will systematically benchmark and analyze the energy consumption of representative ML workloads (e.g., BERT pre-training, GPT-2 fine-tuning, ViTs) and HPC kernels (e.g., 2D/3D stencils, dense matrix multiplies, mini-DFT) on the Cerebras CS-2 wafer-scale engine, using on-chip telemetry and external meters to gather fine-grained metrics—total joules, energy per iteration/epoch/inference, and energy per FLOP—across varied batch sizes and problem scales; it will uncover how compute density, memory access patterns, and communication intensity shape power draw over time, pinpoint energy bottlenecks in phases like initialization or convergence, and propose software- and hardware-level optimizations.

Contact:

Jophin John at LRZ (Jophin.John@lrz.de)

Co-supervized: Prof. Michael Gerndt

This work will be largely run and evaluated on the HPC systems of LRZ, and will also be co-advised by LRZ colleagues.

Background:

We have previously developed a framework for automatic running of various benchmarks, which enables fine-grained level of detail with respect to the configuration of the benchmark and the resources it runs on. There are multiple popular benchmarks included, stressing different aspects of the system, such as memory, cache or compute. More benchmarks can easily be added. As a second step, this framework automatically processes the raw data from the runs to provide basic statistical analysis. Finally, the data is either visualized or it is loaded by the sys-sage library(paper) for further use, such as for scheduling and mapping processes/tasks on resources (nodes, sockets, cores,..). The main focus of the framework is to seamlessly collect performance data and to evaluate performance variations on CPUs in (large-scale production) HPC systems.

Task:

In this thesis, we want to explore characteristics of modern supercomputers and provide a deeper analysis of these – bringing understanding to the performance variations the users of these systems face. You will prepare and run large-scale experiments of the existing benchmarking framework on one or multiple supercomputers (SuperMUC-NG, NG Phase2, MPG, …), and analyze the resulting data. We are interested in multiple aspects:

1. Analyzing the performance variability on (the whole or some reasonable fraction of) the system, to see how much performance variability do users experience.
2. Looking more closely at the supercomputer topology — can we see some differences in performance on the island/rack/chassis-level? If so, can we find something like a “representative node of a rack/island” that would indicate what the expected performance on said island/rack/.. would be? If there is such a node, we could just run the benchmarks on this one node and extrapolate the performance of the entire rack/island.
3. Showcasing the effects on performance, and indicating that the benchmark data can be used for better scheduling. (The import of the data into sys-sage for later use can already be done out-of-the-box but maybe a small updates may be necessary) Very roughly, we would be looking for a use-case, where we use sys-sage to make explicit resource allocation based on the performance variability data (e.g. place performance-critical processes on good-quality nodes/cores). The expected result would see performance improvement over random resource assignment. 

Contact:
In case of interest, please contact Stepan Vanecek (stepan.vanecek at tum.de) of the Chair for Computer Architecture and Parallel Systems (Prof. Schulz) and/or Amir Raoofy (Amir.Raoofy at lrz.de) from LRZ and attach your CV & transcript of records.

Published on 06.03.2025

This work will be largely run and evaluated on the HPC systems of LRZ, and will also be co-advised by LRZ colleagues.

Background:

CAPS TUM has previously developed a framework for automatic running of various benchmarks, which enables fine-grained level of detail with respect to the configuration of the benchmark and the resources it runs on. There are multiple popular benchmarks included, stressing different aspects of the system, such as memory, cache or compute. More benchmarks can easily be added. As a second step, this framework automatically processes the raw data from the runs to provide basic statistical analysis. Finally, the data is either visualized or it is loaded by the sys-sage library(paper) for further use, such as for scheduling and mapping processes/tasks on resources (nodes, sockets, cores,..). The main focus of the framework is to seamlessly collect performance data and to evaluate performance variations on CPUs in (large-scale production) HPC systems.

Parallel to this, LRZ has developed AutoBench, which is a platform for automated and reproducible benchmarking in HPC Testbeds. It is capable of setting and controlling different SW and HW knobs, having more control over the exact configuration of the test system. It enables benchmarking the tested system with different configurations, so that the effect of these configurations can also be analyzed.

Task:

The first part of this thesis lies in integrating these two approaches, so that we can benefit from the fine granularity and performance variations focus of the CAPS tool as well as from the control over the system configuration on from the LRZ side.

Once the integration is in place, there are multiple analyses and experiments to have a look at. Due to time constraints, we will likely restrict the work to one or two of the following:

• Exploring variability in different configurations: can we see some differences in the performance variability of the benchmarks when we run them on differently configured nodes? (do all benchmarks behave the same variability differences or are there differences?)
• Finding optimal configurations for different workloads: do all benchmarks show higher/lower variability with certain config? is some configuration better for some benchmark and another config for another benchmark? For instance, can we find (different) optimal configurations for compute- vs memory-heavy benchmarks/jobs?
• Exploring differences in variability on different configurations and different nodes: Comparing always nodes with identical configuration, are some nodes always performing worse than others regardless of the configuration? Are there some configurations that amplify/reduce the differences in the perf. variability?

Contact:
In case of interest, please contact Stepan Vanecek (stepan.vanecek at tum.de) of the Chair for Computer Architecture and Parallel Systems (Prof. Schulz) and/or Amir Raoofy (Amir.Raoofy at lrz.de) from LRZ and attach your CV & transcript of records.

Published on 06.03.2025

Background:

HPC systems are becoming increasingly heterogeneous as a consequence of the end of Dennard scaling, slowing down of Moore's law, and various emerging applications including LLMs, HPDAs, and others. At the same time, HPC systems consume a tremendous amount of power (can be over 20MW), which requires sophisticated power management schemes at different levels from a node component to the entire system. Driven by those trends, we are studing on sophisticated resource and power management techniques specifically tailored for modern HPC systems, as a part of Regale project (https://regale-project.eu/).

Research Summary:

In this work, we will focus on co-scheduling (co-locating multiple jobs on a node to minimize the resource wastes) and/or power management on HPC systems, with a particular focus on heterogeneous computing systems, consisting of multiple different processors (CPU, GPU, etc.) or memory technologies (DRAM, NVRAM, etc.). Recent hardware components generally support a variety of resource partitioning and power control features, such as cache/bandwidth partitioning, compute resource partitioning, clock scaling, power/temperature capping, and others, controllable via previlaged software. You will first pick up some of them and investigate their impact on HPC applications in performance, power, energy, etc. You will then build an analytical or emperical model to predict the impact and develop a control scheme to optimize the knob setups using your model. You will use hardware available in CAPS Cloud (https://www.ce.cit.tum.de/caps/hw/caps-cloud/) or LRZ Beast machines (https://www.lrz.de/presse/ereignisse/2020-11-06_BEAST/) to conduct your study.

Requirements:

• Basic knowledge/skills on computer architecture, high performance computing, and statistics
• Basic knowledge/skills on surrounding areas would also help (e.g., machine learning, control theory, etc.).
• In genreral, we would be very happy with guiding anyone self-motivated, capable of critical thinking, and curious about computer science.
• We don't want you to be too passive – you are supposed to think/try yourself to some extend, instead of fully following our instructions step by step.
• If your main goal is passing with any grade (e.g., 2.3), we'd suggest you look into a different topic.

See also our former studies:

• Urvij Saroliya, Eishi Arima, Dai Liu, Martin Schulz "Hierarchical Resource Partitioning on Modern GPUs: A Reinforcement Learning Approach" In Proceedings of IEEE International Conference on Cluster Computing (CLUSTER), pp.185-196, Nov. (2023)
• Issa Saba, Eishi Arima, Dai Liu, Martin Schulz "Orchestrated Co-Scheduling, Resource Partitioning, and Power Capping on CPU-GPU Heterogeneous Systems via Machine Learning" In Proceedings of 35th International Conference on Architecture of Computing Systems (ARCS), pp.51-67, Sep. (2022)
• Eishi Arima, Minjoon Kang, Issa Saba, Josef Weidendorfer, Carsten Trinitis, Martin Schulz "Optimizing Hardware Resource Partitioning and Job Allocations on Modern GPUs under Power Caps" In Proceedings of International Conference on Parallel Processing Workshops, no. 9, pp.1-10, Aug. (2022)
• Eishi Arima, Toshihiro Hanawa, Carsten Trinitis, Martin Schulz "Footprint-Aware Power Capping for Hybrid Memory Based Systems" In Proceedings of the 35th International Conference on High Performance Computing, ISC High Performance (ISC), pp.347--369, Jun. (2020)

Contact:

Dr. Eishi Arima, eishi.arima@tum.de, https://www.ce.cit.tum.de/caps/mitarbeiter/eishi-arima/

Prof. Dr. Martin Schulz

Description:
Benchmarks are an essential tool for performance assessment of HPC systems. During the pro-
curement process of HPC systems both benchmarks and proxy applications are used to assess
the system which is to be procured. New generations of HPC systems often serve the current
and evolving needs of the applications for which the system is procured. Therefore, with new
generations of HPC systems, the selected proxy application and benchmarks to assess the sys-
tems’ performance are also selected for the specific needs of the system. Only a few of these
have stayed persistent over longer time periods. At the same time the quality of benchmarks
is typically not questioned as they are seen to only be representatives of specific performance
indicators.

This work aims to provide a more systematic approach with the goal of evaluating benchmarks
targeting the memory subsystem, looking at capacity latency and bandwidth.
 

Problem statement:
How can benchmarks used to assess memory performance, including cache usage, be system-
atically compared amongst each others?

Project Description

Description:
Benchmarks are an essential tool for performance assessment of HPC systems. During the
procurement process of HPC systems both benchmarks and proxy applications are used to as-
sess the system which is to be procured. With new generations of HPC systems, the selected
proxy application and benchmarks are often exchanged and benchmarks for specific needs of
the system are selected. Only a few of these have stayed persistent over longer time periods. At
the same time the quality of benchmarks is typically not questioned as they are seen to only be
representatives of specific performance indicators.

This work targets to provide a more systematic approach with the goal of evaluating bench-
marks targeting Network performance, namely regarding MPI (Message Passing Interface) in
both functional test as well as for benchmark applications.

Problem statement:
How can benchmarks used to assess Network performance, using MPI routines, be systemati-
cally compared amongst each others?

Project Description

Description:
Benchmarks are an essential tool for performance assessment of HPC systems. During the pro-
curement process of HPC systems both benchmarks and proxy applications are used to assess
the system which is to be procured. New generations of HPC systems often serve the current
and evolving needs of the applications for which the system is procured. Therefore, with new
generations of HPC systems, the selected proxy application and benchmarks to assess the sys-
tems’ performance are also selected for the specific needs of the system. Only a few of these
have stayed persistent over longer time periods. At the same time the quality of benchmarks
is typically not questioned as they are seen to only be representatives of specific performance
indicators.

This work aims to evaluate benchmarks for input and output (I/O) performance to provide a
systematic approach to evaluate benchmarks targeting read and write performance of different
characteristics as seen in application behavior, mimiced by benchmarks.
 

Problem statement:
How can benchmarks used to assess I/O performance be systematically compared amongst
each others?

Thesis Description

Background

Performance Monitoring Units (PMUs) are integral to modern processor architectures, providing detailed insights into system performance through mechanisms like Precise Event-Based Sampling (PEBS). PEBS enables precise attribution of performance events to specific instructions, making it a critical tool for software optimization and system profiling. Intel's Skylake (6th generation) and Icelake (10th generation) microarchitectures implement PEBS, but changes in PEBS configuration between these generations have introduced compatibility challenges. These changes affect the availability and format of performance data, breaking existing implementations designed for Skylake and older architectures.

The Mitos tool, developed by our research group, is a specialized performance analysis tool that leverages PEBS to collect high-precision performance samples. Mitos has a robust implementation that performs effectively on Skylake and earlier Intel architectures. However, due to changes in the hardware design and the functionality of the PMUs, Mitos fails to collect accurate samples on these newer processors. This thesis aims to address this gap by extending Mitos to support Icelake, ensuring its continued relevance across modern Intel architectures.

Context

The Mitos tool is designed to facilitate detailed performance analysis in applications ranging from high-performance computing to system-level optimization. Its reliance on PEBS makes it sensitive to architectural changes in Intel processors, such as those introduced in Icelake. These changes may include modifications to PEBS event types, sampling modes, buffer formats, or hardware counter configurations. As Intel continues to evolve its processor designs, ensuring Mitos’ compatibility with newer architectures like Icelake is essential for maintaining its utility in performance monitoring and research. This thesis provides an opportunity to enhance Mitos by adapting its PEBS sample collection mechanism to handle recent architectures, such as Icelake, seamlessly.

Goals

The primary objective of this thesis is to extend the Mitos tool to support accurate and efficient PEBS sample collection on Icelake architectures while preserving its functionality on Skylake. The specific goals are as follows:

1. Analyze PEBS Configuration Changes: Investigate the differences in PEBS implementation between Skylake and Icelake architectures. This involves studying Intel’s documentation (e.g., Software Developer’s Manual), analyzing Mitos’ existing Skylake implementation, and conducting experiments to identify Icelake-specific changes in event support, sampling behavior, or data formats.
2. Adapt Mitos’ Implementation: Modify Mitos’ PEBS sample collection mechanism to support Icelake architectures. This may involve updating configuration parameters, handling new PEBS buffer formats, or implementing architecture-specific code paths to ensure compatibility with both Skylake and Icelake.
3. Validate and Test the Updated Tool: Test the adapted Mitos implementation on Skylake and Icelake systems to verify correctness, accuracy, and performance. Validation will include comparing collected samples against known benchmarks and ensuring seamless integration with Mitos’ existing features.
4. Optional Comparative Analysis: If time permits, conduct a comparative analysis of PEBS data collected by Mitos on Skylake and Icelake. This could explore differences in sampling accuracy, performance overhead, or event coverage, providing insights into the practical implications of Icelake’s PEBS changes.

Expected Outcomes

By the end of this thesis, the student will deliver:

• A detailed report documenting the PEBS configuration differences between Skylake and Icelake and their impact on Mitos.
• An updated version of Mitos with a PEBS sample collection implementation compatible with both Skylake and Icelake architectures.
• Comprehensive tests validating Mitos’ performance and accuracy on both architectures.
• (Optional) A comparative study analyzing PEBS data collected by Mitos on Skylake and Icelake, highlighting architectural impacts.

Significance

This thesis will enhance the Mitos tool’s applicability by ensuring its compatibility with Icelake (and in general newer architectures). The updated implementation will enable researchers and developers to perform precise performance analysis across a broader range of processors, supporting applications in software optimization, system profiling, and performance research. Additionally, the findings will contribute to a deeper understanding of PMU evolution in Intel architectures, informing future adaptations of Mitos and similar tools.

Prerequisites

• Proficiency in low-level programming (e.g., C/C++) and experience with Linux performance analysis tools (e.g., perf).
• Basic understanding of Intel processor architectures and PMU documentation.
• (Preferred) Familiarity with computer architecture, PMUs, and performance monitoring concepts.

Contact

In case of interest, please contact Stepan Vanecek (stepan.vanecek at tum.de) of the Chair for Computer Architecture and Parallel Systems (Prof. Schulz) and attach your CV & transcript of records.

Published on 16.06.2025

Background

Predicting software performance on future computer systems is a critical challenge, particularly for systems that don’t yet exist or aren’t accessible for direct testing. The Structural Simulation Toolkit (SST) is an open-source simulator designed to model complex computing systems, including processors, memory hierarchies, and interconnects. Its Ariel component simulates CPU execution, while MemHierarchy models memory system behavior, enabling the study of data access patterns such as load/store latencies and cache hit/miss events. These patterns are essential for understanding how applications will perform on next-generation hardware.

Our group’s Mitos tool excels at collecting performance data on real hardware using Performance Monitoring Units (PMUs), but it cannot measure hypothetical or unavailable systems. SST addresses this by simulating future architectures, allowing us to generate comparable data. This thesis focuses on developing a mechanism within SST to collect detailed data access pattern traces, leveraging Ariel and MemHierarchy to capture metrics like load latencies, cache levels, and memory access types.

Context

Simulating data access patterns is vital for optimizing software for emerging hardware, especially in domains like high-performance computing and system design. SST’s modular architecture makes it an ideal platform for modeling future systems, but generating detailed memory access traces requires custom integration of its components. This project aims to create a data collection mechanism in SST that produces traces comparable to Mitos’ output on real hardware, enabling performance analysis for systems we can’t yet measure directly. For master students, there’s an opportunity to explore cutting-edge heterogeneous memory systems using Compute Express Link (CXL) version 3.0+ with memory pooling across multiple nodes. This project is a chance to dive into advanced simulation tech and help shape the future of performance analysis!

Goals

The primary goal is to design and implement a data collection mechanism in SST to generate traces of data access patterns, including metrics like load latencies, cache levels, and memory access types. The tasks are tailored to balance expectations for bachelor and master students, with advanced objectives marked as optional for bachelor students and required for master students:

1. Investigate SST’s Capabilities (Bachelor & Master): Explore the Ariel and MemHierarchy components to understand how they model processor and memory interactions. Identify how to extract data access information, such as load/store latencies and cache hit/miss events, by studying SST documentation and running simple simulations.
2. Design a Data Collection Mechanism (Bachelor & Master): Develop a plan for a new module or extension to SST’s Ariel and MemHierarchy components to collect and record data access pattern traces. The design should focus on capturing key metrics (e.g., load latencies, cache levels) in a clear, usable format.
3. Implement the Mechanism (Bachelor & Master): Build the data collection mechanism within SST, likely by modifying or hooking into Ariel and MemHierarchy. For bachelor students, the implementation should focus on core functionality (e.g., capturing basic load/store events), ensuring it’s efficient and integrates with SST. Master students are expected to implement a more robust solution and optimizing for simulation performance.
4. Validate the Traces (Bachelor & Master): Test the mechanism by simulating various workloads in SST. For bachelor students, validation should confirm that the traces accurately capture basic metrics (e.g., load latencies) and align with expected behavior. Master students should additionally compare the traces to Mitos-collected data from real systems (where feasible) to ensure consistency and analyze any discrepancies.
5. Analyze and Optimize (Optional for Bachelor, Expected for Master): Conduct a detailed analysis of the generated traces to extract insights about data access patterns on simulated future architectures, identifying performance trends (e.g., cache bottlenecks) and comparing results to known hardware behaviors. Master students are expected to optimize the implementation for scalability (e.g., handling large workloads). Additionally, master students should investigate simulating heterogeneous memory systems using CXL (version 3.0+ with memory pooling across multiple nodes), modeling off-node memory accesses and analyzing their impact on data access patterns. Bachelor students may attempt this analysis and CXL exploration if time allows but are not required to.

Expected Outcomes

By the end, you’ll deliver:

• A report detailing the data collection mechanism, its integration with SST’s Ariel and MemHierarchy, and (for master students) considerations for CXL-based heterogeneous memory systems.
• A working implementation of the trace collection module in SST, producing usable data access traces.
• (Optional) A test suite validating the accuracy and functionality of the traces for simulated workloads.
• (For Master, Optional for Bachelor) An analysis of the traces, including performance insights and, for master students, findings from simulating CXL-based memory systems.

Why It Matters

This project will enhance SST’s ability to simulate data access patterns for future hardware, helping developers optimize software for systems that aren’t even built yet. Your work will bridge the gap between real-hardware tools like Mitos and simulated environments, with master students pushing the boundaries by exploring next-gen CXL memory systems. It’s a great opportunity to work with cutting-edge tech and make a real impact on performance analysis!

What You’ll Need

• Some interest in computer architecture or simulation concepts (you’ll pick it up as you go!).
• Comfort with coding in C++ (SST’s main language) and maybe some scripting for data analysis.
• Curiosity about SST, Ariel, MemHierarchy, and (for master students) CXL technology (we’ll provide resources to get started).
• Bonus: Experience with performance analysis or tools like Mitos is helpful but not required.

References

• Structural Simulation Toolkit (SST) documentation and tutorials.
• Ariel and MemHierarchy component manuals (available in SST documentation).
• Compute Express Link (CXL) Specification, version 3.0+ (for master students).

Contact

In case of interest, please contact Stepan Vanecek (stepan.vanecek at tum.de) of the Chair for Computer Architecture and Parallel Systems (Prof. Schulz) and attach your CV & transcript of records.

Published on 16.06.2025

Background and Context

Plasma simulations play a pivotal role in advancing research in fusion energy, astrophysics, and materials science by modeling complex physical phenomena. These simulations rely on computationally intensive codes that demand high performance, often leveraging GPU acceleration to meet computational requirements. GPUscout, a specialized tool developed within our research group, is designed to analyze codebases and provide actionable recommendations for performance optimization, particularly for GPU-accelerated applications. Our group works on a large-scale Plasma code, which serves as a critical testbed for evaluating and enhancing GPUscout’s capabilities.

This thesis offers students the opportunity to contribute to high-performance computing (HPC) research by integrating GPUscout with a real-world Plasma code. The work focuses on two primary objectives: (1) ensuring that GPUscout can effectively analyze the Plasma code, adapting the tool as necessary, and (2) applying GPUscout’s recommendations to optimize the Plasma code for improved performance. The scope and depth of the tasks will vary depending on whether the thesis is pursued at the bachelor’s or master’s level, with additional subtasks and deeper analysis required for the master’s thesis.

Objectives

The thesis aims to achieve the following goals:

1. GPUscout Compatibility Analysis and Adaptation
   • Evaluate GPUscout’s ability to analyze the Plasma code, identifying any limitations or compatibility issues.
   • If necessary, adapt GPUscout to ensure effective analysis, which may involve modifying input formats, resolving dependency issues, or extending GPUscout’s functionality.
   • Document the analysis process and any adaptations made to ensure reproducibility.
2. Performance Optimization of the Plasma Code
   • Apply GPUscout’s recommendations to implement performance optimizations in the Plasma code, targeting GPU-specific enhancements such as memory management, kernel optimization, or parallelization improvements.
   • Measure and evaluate the performance impact of the optimizations.

Expected Outcomes

The thesis should deliver a functional pipeline for analyzing the Plasma code with GPUscout, including any necessary adaptations, and a set of implemented optimizations with documented performance results. Students are expected to produce a clear report detailing the analysis process, adaptations, optimizations, and benchmark outcomes.

Prerequisites

• Basic programming skills in C/C++/CUDA and familiarity with Linux environments are required.
• For tasks involving GPU optimizations, experience with GPU programming (CUDA) is beneficial but not mandatory.
• Master’s students are expected to have strong programming skills in C/C++, experience with GPU programming, and familiarity with HPC concepts and profiling tools. Knowledge of Plasma simulation frameworks or numerical methods is advantageous.

Significance

This thesis contributes to the advancement of HPC by improving the performance of a critical Plasma simulation code and enhancing GPUscout’s utility as a performance analysis tool. Students will gain hands-on experience with state-of-the-art tools and techniques, addressing real-world challenges in scientific computing. The results may inform future optimizations in similar HPC applications and strengthen GPUscout’s applicability across diverse codebases.

Contact

In case of interest, please contact Stepan Vanecek (stepan.vanecek at tum.de) of the Chair for Computer Architecture and Parallel Systems (Prof. Schulz) and attach your CV & transcript of records.

Published on 16.06.2025

LAIK is a new programming abstraction developed at LRR-TUM

• Decouple data decompositionand computation, while hiding communication
• Applications work on index spaces
• Mapping of index spaces to nodes can be adaptive at runtime
• Goal: dynamic process management and fault tolerance
• Current status: works on standard MPI, but no dynamic support

Task 1: Port LAIK to Elastic MPI

• New model developed locally that allows process additions and removal
• Should be very straightforward

Task 2: Port LAIK to ULFM

• Proposed MPI FT Standard for “shrinking” recovery, prototype available
• Requires refactoring of code and evaluation of ULFM

Task 3: Compare performance with direct implementations of same models on MLEM

• Medical image reconstruction code
• Requires porting MLEM to both Elastic MPI and ULFM

Task 4: Comprehensive Evaluation

ULFM (User-Level Fault Mitigation) is the current proposal for MPI Fault Tolerance

• Failures make communicators unusable
• Once detected, communicators an be “shrunk”
• Detection is active and synchronous by capturing error codes
• Shrinking is collective, typically after a global agreement
• Problem: can lead to deadlocks

Alternative idea

• Make shrinking lazy and with that non-collective
• New, smaller communicators are created on the fly

Tasks:

• Formalize non-collective shrinking idea
• Propose API modifications to ULFM
• Implement prototype in Open MPI
• Evaluate performance
• Create proposal that can be discussed in the MPI forum

ULFM works on the classic MPI assumptions

• Complete communicator must be working
• No holes in the rank space are allowed
• Collectives always work on all processes

Alternative: break these assumptions

• A failure creates communicator with a hole
• Point to point operations work as usual
• Collectives work (after acknowledgement) on reduced process set

Tasks:

• Formalize“hole-y” shrinking
• Proposenew API
• Implement prototype in Open MPI
• Evaluate performance
• Create proposal that can be discussed in the MPI Forum

With MPI 3.1, MPI added a second tools interface: MPI_T

• Access to internal variables 
• Query, read, write
• Performance and configuration information
• Missing: event information using callbacks
• New proposal in the MPI Forum (driven by RWTH Aachen)
• Add event support to MPI_T
• Proposal is rather complete

Tasks:

• Implement prototype in either Open MPI or MVAPICH
• Identify a series of events that are of interest
• Message queuing, memory allocation, transient faults, …
• Implement events for these through MPI_T
• Develop tool using MPI_T to write events into a common trace format
• Performance evaluation

Possible collaboration with RWTH Aachen

PMIxis a proposed resource management layer for runtimes (for Exascale)

• Enables MPI runtime to communicate with resource managers
• Come out of previous PMI efforts as well as the Open MPI community
• Under active development / prototype available on Open MPI

Tasks: 

• Implement PMIx on top of MPICH or MVAPICH
• Integrate PMIx into SLURM
• Evaluate implementation and compare to Open MPI implementation
• Assess and possible extend interfaces for tools 
• Query process sets

MPI was originally intended as runtime support not as end user API

• Several other programming models use it that way
• However, often not first choice due to performance reasons
• Especially task/actor based models require more asynchrony

Question: can more asynchronmodels be added to MPI

• Example: active messages

Tasks:

• Understand communication modes in an asynchronmodel
• Charm++: actor based (UIUC)•Legion: task based (Stanford, LANL)
• Propose extensions to MPI that capture this model better
• Implement prototype in Open MPI or MVAPICH
• Evaluation and Documentation

Possible collaboration with LLNL and/or BSC

Background

Quantum computing faces a critical challenge: the high error rates of qubits. Quantum error correction (QEC) codes (e.g., surface codes) protect quantum information through redundancy and real-time error mitigation. However, practical implementations require efficient hardware platforms. FPGAs, with their parallel processing capabilities and low latency, are ideal for prototyping QEC schemes. This project aims to implement a QEC code (e.g., surface code) on an FPGA and explore its potential for real-time error correction.

Task

1. Study the principles of QEC codes; investigate decoding algorithms for QEC (e.g., minimum-weight perfect matching (MWPM), QULATIS…)    

2. Hardware Implementation:

• Design and implement the decoder on an FPGA.
• Optimize resource utilization (logic units, memory) and latency, leveraging FPGA parallelism.

3. Performance Evaluation:

• Analyze error correction success rates, latency, and resource efficiency via simulations and hardware testing.
• Compare the impact of code distances on the correction performance.

Requirement

Experience in programming with VHDL/Verilog. Understand basic quantum theory.

Contact:
In case of interest or any questions, please contact Xiaorang Guo (xiaorang.guo@tum.de) at the Chair for Computer Architecture and Parallel Systems (Prof. Schulz) and attach your CV & transcript of records.

Background: Neutral atom (NA) detection plays a crucial role in NA quantum computer in terms of state preparation and readout. Traditional detection methods often rely on computationally intensive image processing techniques that can be inefficient for real-time applications. Implementing an ML-based detection algorithm on FPGA provides a hardware-accelerated solution with low latency, high throughput, and energy efficiency, making it suitable for large-scale atom array experiments.

Tasks

1. Evaluate various ML models (e.g., CNNs, Mamba models) and train them on labeled atom datasets.   

2. Hardware Implementation:

• Optimize the trained model for FPGA deployment, eg, with tiling or tensor core-based architectures
• Aim to balence the resource utilization (logic units, memory) and latency, leveraging FPGA parallelism.

3. Performance Evaluation:

• Compare accuracy, inference latency with C++/python based methods

Required Skills & Resources:

• Have backgrounds in ML
• Experience with FPGA programming (e.g., VHDL, Verilog, or HLS)
• Familiarity with PYNQ, Xilinx tools, or equivalent platforms

Contact: Xiaorang Guo(xiaorang.guo(at)tum.de), Jonas Winklmann (jonas.winklmann(at)tum.de), Prof. Martin Schulz

If you have interests regarding the following topics, and would like to know how to implement efficient AI or how to implement AI on different hardware setups, such as:

1. DL Application on Heteragenous system
2. Network Compression
3. ML and Architecture
4. AI for Quantum
5. AI on Hardware (e.g. restricted edge devices, Cerebras)

Please feel free to contact dai.liu@tum.de for MA, BA, GR.