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Among the goals of the seminar is to give a good overview to the participants about the complete design flow of an FPGA: from design entry level to analysis and verification. Students will get an opportunity to deepen into one of the aspects of the design process and also try things out themselves where possible.

It is planned to cover a broad spectrum of FPGA topics including Hardware Description Languages, Synthesis, Applications in HPC, FPGA Architectures, Development Tools, etc.

In the context of the topics, mentioned above, students are expected to investigate the current trends, discuss the available options, potential advantages and drawbacks of the alternatives and preferably present some small demo related to their topic. The work will also include an around a 10-page report and a 20 minutes presentation, concluding with 15-20 minutes discussion.