Foto von Alexander Hepp

Alexander Hepp

Technische Universität München

Dienstort

Lehrstuhl für Sicherheit in der Informationstechnik (Prof. Sigl)

Work:
Theresienstr. 90(0101)/1.ZG
80333 München

Forschungsgebiete

  • Hardware trojan design/identification
  • Netlist reverse engineering
  • Neuro engineering

Lehre

Blockpraktikum C++

Vortragende/r (Mitwirkende/r)
Nummer0000004097
Art
Umfang4 SWS
SemesterWintersemester 2021/22
UnterrichtsspracheDeutsch
Stellung in StudienplänenSiehe TUMonline
TermineSiehe TUMonline

Teilnahmekriterien

Siehe TUMonline
Anmerkung: Bachelorstudiengang EI; Voraussetzung für die Teilnahme ist die Anmeldung zur Prüfung

Lernziele

Nach der Teilnahme an der Modulveranstaltung haben die Studierenden Grundlagen und erweiterte Kenntnisse in der Programmiersprache C++ erworben und sind in der Lage ihr Wissen praktisch anzuwenden. Auch können die Studierenden Template Klassen und Funktionen entwickeln und die Standard Template Library (STL) im Rahmen von Programmieraufgaben mit C++ anwenden. Sie haben die Bedeutung guter Lesbaren und gut Dokumentation von Code verstanden und sind in der Lage solchen Code in C++ zu entwickeln. Zudem haben die Studierenden die Konzepte der objektorientierte Programmierung (OOP) verstanden und sind in der Lage, auf Basis dieser Konzepte eigene objektorientierte Programme - unter Verwendung von Klassen, Vererbung, Polymorphie, virtuelle Funktionen, etc. - in der Programmiersprache C++ zu entwickeln.

Beschreibung

Im Rahmen des Elektrotechnik-Studiums ist eine Ausbildung in einer führenden, in der Industrie weit verbreiteten Programmiersprache wie C++ unabdingbar. Dieses Blockpraktikum zum Thema C++ wird in den Semesterferien angeboten. Es gliedert sich in einen Grundlagen- und einen Projektteil. Im Grundlagenteil werden fundamentale Sprachkonzepte von C++, wie Objekte, Klassen und Templates, sowie grundlegende Regeln eines guten Programmierstiels in Vorlesungen erklärt und anschließend anhand praktischer Übungsbeispiele umgesetzt und vertieft. Dieser Grundlagenteil wird in 2 Wochen Vollzeit bearbeitet. Dabei stehen bei den praktischen Übungen stets Tutoren für Fragen zur Verfügung. Im zweiten Teil sollen die Lehrinhalte vertieft werden, indem in Kleingruppen ein Projekt umgesetzt wird. Hierfür haben die Studierenden 2 Wochen Zeit, und können sowohl zu Hause als auch in den Räumen des Lehrstuhls arbeiten. Die Bewertung wird in Form einer schriftlichen und einer mündlichen Prüfung durchgeführt.

Inhaltliche Voraussetzungen

Grundpraktikum C, Algorithmen und Datenstrukturen oder vergleichbare Vorlesung

Lehr- und Lernmethoden

Vorlesung mit anschließenden praktischen Übungen im Labor in der ersten Phase, Eigenstudium in der zweiten Phase

Studien-, Prüfungsleistung

- Das Verständnis der in der Vorlesung und der praktischen Übung im ersten Teil vermittelten Wissens wird während der zweiten Hälfte des vierwöchigen Blocks in Form einer 60 minütigen schriftlichen Prüfung nachgewiesen. - Die Fähigkeit zur praktischen Umsetzung des Erlernten wird durch die erfolgreiche Durchführung einer praktischen Arbeit nachgewiesen. - Die Qualität der praktischen Arbeit wird durch eine Präsentation der im Praktikum durchzuführenden Projektarbeit und eine gezielte Befragung zur abgegebenen C++-Implementierung am Ende des Blockpraktikums mündlich nachgewiesen (Dauer ca. 30 Minuten). Endnote: 60% schriftliche Klausur + 40% Benotung von Präsentation und Diskussion. Die praktische Arbeit muss als "bestanden" sein. Die Endnote setzt sich zu 60% aus der schriftliche Klausur und zu 40% aus der Benotung von Präsentation und Beantwortung der mündlichen Fragen zusammen. Die praktische Arbeit muss als "bestanden" bewertet sein.

Empfohlene Literatur

Programming - Principles and Practice Using C++, Addison-Wesley ISBN 978-0321543721. December 2008. The C++ Programming Language (Third Edition and Special Edition) Addison-Wesley, ISBN 0-201-88954-4 and 0-201-70073-5. Fundamental Algorithms The Art of Computer Programming Addison-Wesley, ISBN 0-201-89683-4

Links

Offene Arbeiten für Studenten

Bachelorarbeiten

Exploring netlist representations for netlist RE

Beschreibung

Reverse engineering of silicon hardware designs is an interesting task for various applications in science and industry, such as patent infringement detection, security analysis or hardware trojan detection.

One of the most challenging tasks is to go from the flat netlist, that is a graph of logic gates and wires between them, to a high level description of the design.

In this work, you will analyze and compare different methods for representing a netlist and the benefits and problems when analyzing the netlist using the different representations

 

Voraussetzungen

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in a python to use our existing framework
  • Basic knowledge of a hardware description language such as vhdl or verilog to understand what you are analyzing
  • Basic knowledge in graph theory, algorithms etc. to cope with problems on the way.

 

Kontakt

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

 

Betreuer:

Alexander Hepp

Bringing a RISC-V to Life: Implementation of tooling for a RISC-V CPU

Beschreibung

RISC-V is the upcoming instruction set architecture of the future. We have taped out our own RISC-V chip for security purposes.

Your task is to implement various testing routines for a RISC-V CPU existing at the chair.

Voraussetzungen

This list is not final, rather a guideline for the competences required for successfully completing the project.

  • Sufficient knowledge of C
  • Experience with embedded programming and environment
  • Some knowledge of cmake, as compilation works via cmake
  • Some knowledge of python, as tooling is partially implemented with it.

Betreuer:

Alexander Hepp

Masterarbeiten

Exploring netlist representations for netlist RE

Beschreibung

Reverse engineering of silicon hardware designs is an interesting task for various applications in science and industry, such as patent infringement detection, security analysis or hardware trojan detection.

One of the most challenging tasks is to go from the flat netlist, that is a graph of logic gates and wires between them, to a high level description of the design.

In this work, you will analyze and compare different methods for representing a netlist and the benefits and problems when analyzing the netlist using the different representations

 

Voraussetzungen

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in a python to use our existing framework
  • Basic knowledge of a hardware description language such as vhdl or verilog to understand what you are analyzing
  • Basic knowledge in graph theory, algorithms etc. to cope with problems on the way.

 

Kontakt

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

 

Betreuer:

Alexander Hepp

Forschungspraxis (Research Internships)

Exploring netlist representations for netlist RE

Beschreibung

Reverse engineering of silicon hardware designs is an interesting task for various applications in science and industry, such as patent infringement detection, security analysis or hardware trojan detection.

One of the most challenging tasks is to go from the flat netlist, that is a graph of logic gates and wires between them, to a high level description of the design.

In this work, you will analyze and compare different methods for representing a netlist and the benefits and problems when analyzing the netlist using the different representations

 

Voraussetzungen

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in a python to use our existing framework
  • Basic knowledge of a hardware description language such as vhdl or verilog to understand what you are analyzing
  • Basic knowledge in graph theory, algorithms etc. to cope with problems on the way.

 

Kontakt

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

 

Betreuer:

Alexander Hepp

Ingenieurpraxis

Exploring netlist representations for netlist RE

Beschreibung

Reverse engineering of silicon hardware designs is an interesting task for various applications in science and industry, such as patent infringement detection, security analysis or hardware trojan detection.

One of the most challenging tasks is to go from the flat netlist, that is a graph of logic gates and wires between them, to a high level description of the design.

In this work, you will analyze and compare different methods for representing a netlist and the benefits and problems when analyzing the netlist using the different representations

 

Voraussetzungen

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in a python to use our existing framework
  • Basic knowledge of a hardware description language such as vhdl or verilog to understand what you are analyzing
  • Basic knowledge in graph theory, algorithms etc. to cope with problems on the way.

 

Kontakt

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

 

Betreuer:

Alexander Hepp

Bringing a RISC-V to Life: Implementation of tooling for a RISC-V CPU

Beschreibung

RISC-V is the upcoming instruction set architecture of the future. We have taped out our own RISC-V chip for security purposes.

Your task is to implement various testing routines for a RISC-V CPU existing at the chair.

Voraussetzungen

This list is not final, rather a guideline for the competences required for successfully completing the project.

  • Sufficient knowledge of C
  • Experience with embedded programming and environment
  • Some knowledge of cmake, as compilation works via cmake
  • Some knowledge of python, as tooling is partially implemented with it.

Betreuer:

Alexander Hepp

Studentische Hilfskräfte

Exploring netlist representations for netlist RE

Beschreibung

Reverse engineering of silicon hardware designs is an interesting task for various applications in science and industry, such as patent infringement detection, security analysis or hardware trojan detection.

One of the most challenging tasks is to go from the flat netlist, that is a graph of logic gates and wires between them, to a high level description of the design.

In this work, you will analyze and compare different methods for representing a netlist and the benefits and problems when analyzing the netlist using the different representations

 

Voraussetzungen

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in a python to use our existing framework
  • Basic knowledge of a hardware description language such as vhdl or verilog to understand what you are analyzing
  • Basic knowledge in graph theory, algorithms etc. to cope with problems on the way.

 

Kontakt

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

 

Betreuer:

Alexander Hepp

Aktuelle Veröffentlichungen

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Hinweis: Die „Schnellsuche“ findet nur Text in den angezeigten Feldern; nicht in Abstracts oder Schlagwörtern. Der Suchbegriff muss mindestens 3 Buchstaben lang sein.

2022

  • Aksoy, Levent and Hepp, Alexander and Baehr, Johanna and Pagliarini, Samuel: Hardware Obfuscation of Digital FIR Filters. 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, IEEE, 2022Prague, Czech Republic, 68-73 mehr… BibTeX Volltext ( DOI )
  • Brunner, Michaela and Hepp, Alexander and Baehr, Johanna and Sigl, Georg: Toward a Human-Readable State Machine Extraction. ACM Trans. Des. Autom. Electron. Syst. 27 (6), 2022 mehr… BibTeX Volltext ( DOI )
  • Hepp, Alexander and Baehr, Johanna and Sigl, Georg: Golden Model-Free Hardware Trojan Detection by Classification of Netlist Module Graphs. Design, Automation and Test in Europe Conference, IEEE, 2022Antwerp, Belgium, 1317-1322 mehr… BibTeX Volltext ( DOI )
  • Lippmann, Bernhard and Ludwig, Matthias and Mutter, Johannes and Bette, Ann-Christin and Hepp, Alexander and Baehr, Johanna and Rasche, Martin and Kellermann, Oliver and Gieser, Horst and Zweifel, Tobias and Kovac, Nicola: Physical and Functional Reverse Engineering Challenges for Advanced Semiconductor Solutions. 2022 Design, Automation & Test in Europe Conference & Exhibition DATE, IEEE, 2022Antwerp, Belgium mehr… BibTeX

2021

  • Hepp, Alexander and Sigl, Georg: Tapeout of a RISC-V Crypto Chip with Hardware Trojans: A Case-Study on Trojan Design and Pre-Silicon Detectability. Proceedings of the 18th ACM International Conference on Computing Frontiers (CF '21), Association for Computing Machinery, 2021Virtual: Catania, Italy mehr… BibTeX Volltext ( DOI )
  • Ludwig, Matthias and Hepp, Alexander and Brunner, Michaela and Baehr, Johanna: CRESS: Framework for Vulnerability Assessment of Attack Scenarios in Hardware Reverse Engineering. 2021 IEEE Physical Assurance and Inspection of Electronics (PAINE), 2021Washington DC, US mehr… BibTeX Volltext ( DOI )

Kostenlose Volltexte für ausgewählte Veröffentlichungen

Sie können hier die Volltexte meiner Publikationen kostenlos herunterladen
10.1145/3457388.3458869 Tapeout of a RISC-V crypto chip with hardware trojans
10.1109/PAINE54418.2021.9707695 CRESS: Framework for Vulnerability Assessment of Attack Scenarios in Hardware Reverse Engineering
10.1145/3513086 Towards a Human-readable State Machine Extraction
DDECS 2022 (wird veröffentlicht) Hardware Obfuscation of Digital FIR Filters (Best Paper Award)