Reverse engineering of silicon hardware designs is an interesting task for various applications in science and industry, such as patent infringement detection, security analysis or hardware trojan detection.

One of the most challenging tasks is to go from the flat netlist, that is a graph of logic gates and wires between them, to a high level description of the design.

In this work, you will analyze and compare different methods for representing a netlist and the benefits and problems when analyzing the netlist using the different representations

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in a python to use our existing framework
• Basic knowledge of a hardware description language such as vhdl or verilog to understand what you are analyzing
• Basic knowledge in graph theory, algorithms etc. to cope with problems on the way.

RISC-V is the upcoming instruction set architecture of the future. We have taped out our own RISC-V chip for security purposes.

Your task is to implement various testing routines for a RISC-V CPU existing at the chair.

This list is not final, rather a guideline for the competences required for successfully completing the project.

• Sufficient knowledge of C
• Experience with embedded programming and environment
• Some knowledge of cmake, as compilation works via cmake
• Some knowledge of python, as tooling is partially implemented with it.

Reverse engineering of silicon hardware designs is an interesting task for various applications in science and industry, such as patent infringement detection, security analysis or hardware trojan detection.

One of the most challenging tasks is to go from the flat netlist, that is a graph of logic gates and wires between them, to a high level description of the design.

In this work, you will analyze and compare different methods for representing a netlist and the benefits and problems when analyzing the netlist using the different representations

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in a python to use our existing framework
• Basic knowledge of a hardware description language such as vhdl or verilog to understand what you are analyzing
• Basic knowledge in graph theory, algorithms etc. to cope with problems on the way.

Reverse engineering of silicon hardware designs is an interesting task for various applications in science and industry, such as patent infringement detection, security analysis or hardware trojan detection.

One of the most challenging tasks is to go from the flat netlist, that is a graph of logic gates and wires between them, to a high level description of the design.

In this work, you will analyze and compare different methods for representing a netlist and the benefits and problems when analyzing the netlist using the different representations

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in a python to use our existing framework
• Basic knowledge of a hardware description language such as vhdl or verilog to understand what you are analyzing
• Basic knowledge in graph theory, algorithms etc. to cope with problems on the way.

Reverse engineering of silicon hardware designs is an interesting task for various applications in science and industry, such as patent infringement detection, security analysis or hardware trojan detection.

One of the most challenging tasks is to go from the flat netlist, that is a graph of logic gates and wires between them, to a high level description of the design.

In this work, you will analyze and compare different methods for representing a netlist and the benefits and problems when analyzing the netlist using the different representations

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in a python to use our existing framework
• Basic knowledge of a hardware description language such as vhdl or verilog to understand what you are analyzing
• Basic knowledge in graph theory, algorithms etc. to cope with problems on the way.

RISC-V is the upcoming instruction set architecture of the future. We have taped out our own RISC-V chip for security purposes.

Your task is to implement various testing routines for a RISC-V CPU existing at the chair.

This list is not final, rather a guideline for the competences required for successfully completing the project.

• Sufficient knowledge of C
• Experience with embedded programming and environment
• Some knowledge of cmake, as compilation works via cmake
• Some knowledge of python, as tooling is partially implemented with it.

Reverse engineering of silicon hardware designs is an interesting task for various applications in science and industry, such as patent infringement detection, security analysis or hardware trojan detection.

One of the most challenging tasks is to go from the flat netlist, that is a graph of logic gates and wires between them, to a high level description of the design.

In this work, you will analyze and compare different methods for representing a netlist and the benefits and problems when analyzing the netlist using the different representations

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in a python to use our existing framework
• Basic knowledge of a hardware description language such as vhdl or verilog to understand what you are analyzing
• Basic knowledge in graph theory, algorithms etc. to cope with problems on the way.