- Post-Quantum Signatures on RISC-V with Hardware Acceleration. ACM Trans. Embed. Comput. Syst., 2023 mehr… BibTeX Volltext ( DOI )
- Silicon Proven Hardware Acceleration of Post-Quantum Cryptography on RISC-V. RISC-V Summit Europe 2023, RISC-V Europe, 2023 mehr… BibTeX
- FuLeeca: A Lee-Based Signature Scheme. Code-Based Cryptography, Springer Nature Switzerland, 2023CBCrypto 2023: 4th International Workshop on Code-Based Cryptography mehr… BibTeX Volltext ( DOI )
- Multiplierless Design of Very Large Constant Multiplications in Cryptography. Transactions on Circuits and Systems II: Express Briefs, 2022 mehr… BibTeX Volltext ( DOI )
- Hardware Accelerated FrodoKEM on RISC-V. 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), IEEE, 2022Prague, Czech Republic mehr… BibTeX Volltext ( DOI )
- DOMREP – An Orthogonal Countermeasure for Arbitrary Order Side-Channel and Fault Attack Protection. IEEE Transactions on Information Forensics and Security (16), 2021, 4321-4335 mehr… BibTeX Volltext ( DOI )
- Masked Accelerators and Instruction Set Extensions for Post-Quantum Cryptography. IACR Transactions on Cryptographic Hardware and Embedded Systems 2022 (1), 2021, 414-460 mehr… BibTeX Volltext ( DOI )
- Algebraic Fault Analysis of Subterranean 2.0. 2021 Workshop on Fault Detection and Tolerance in Cryptography (FDTC), 2021Milano, Italy mehr… BibTeX Volltext ( DOI )
- A Survey on the Application of Fault Analysis on Lightweight Cryptography. 2021 11th IFIP International Conference on New Technologies, Mobility and Security (NTMS), IEEE, 2021Paris, France mehr… BibTeX Volltext ( DOI )
- A Detailed Report on the Overhead of Hardware APIs for Lightweight Cryptography. Cryptology ePrint Archive, Report 2020/112, 2020 mehr… BibTeX
M.Sc. Patrick Karl
- Tel.: +49 (89) 289 - 28257
- Raum: 0101.Z1.009
- patrick.karl@tum.de
Research Interests
My research focuses on efficient hardware implementations for post-quantum cryptography. More specifically, I am interested in hardware acceleration for digital signature algorithms on RISC-V platforms for embedded systems. This includes not only performance optimizations, but also aims to improve power and energy consumption. Another important aspect is securing implementations against physical attacks, i.e. side-channel and fault-attacks. Besides FPGA prototyping I am also involved in ASIC design and tape-out. Additional interests include advanced cryptographic approaches like homomorphic- or attribute-based encryption. In short:
- Post-Quantum Cryptography
- Efficient Hardware Implementations
- Countermeasures against Physical Attacks
- FPGA and ASIC design
Teaching
- Praktikum ASIC Design von Hardwarebeschleunigern für RISC-V: WS22/23, SS23, WS23/24
- Projektpraktikum Krypto-Implementierung: SS22
- Circuit Design Fundamentals: 2020/21, 2021/22, 2022/23 (TUM ASIA Singapore)
Publications
Talks
- PQC-Update 2023, 2023 (Garching):
"Post-Quantum Signatures on RISC-V with Hardware Acceleration" [link, slides] - TASER workshop, 2022 (Leuven):
"A 22nm ASIC for Flexible Post-Quantum Cryptography" [link] - SAFEST Summer School, 2022 (Montpellier):
"RISC-V: Security with and in an open-source Instruction Set" [link] -
NIST Lightweight Cryptography Workshop, 2020 (virtual):
"A Detailed Report on the Overhead of Hardware APIs for Lightweight Cryptography" [link]