Foto von Manuel Brosch

M.Sc. Manuel Brosch

Research Interests

  • Side-Channel Analysis of Neural Networks, AI Hardware Accelerators and Neuromorphic Hardware
  • Countermeasures against Side-Channel Analysis
  • Secure Implementations of Neural Networks

Open Positions for Students

If you are interested in my research area, feel free to contact me for possible Bachelor Thesis, Master Thesis or research internship.

Master's Theses

SCA of AI Hardware Accelerator

Keywords:
SCA, Neural Networks, Hardware, FPGA

Description

Neural Networks are inevitable in everyday life. Speech and face recognition as well as driverless cars are just some examples where Artificial Neural Networks (ANN) are used. Training a deep ANN is very time-consuming and computational expensive. Thus, the intellectual property stored in an ANN is an asset worth to protect. Additionally, implementations on edge devices need to be power-efficient whilst maintaining a high throughput. [1] or [2] are examples for frameworks aiming to fulfill these requirements.


A side-channel attack can be used to extract the network parameters such as the number or type of layers, as well as weights and bias values. In [3, 4] side-channel attacks on different implementations of ANNs are performed. 

In this work, a side-channel attack on autogenerated implementations of different ANNs should be performed. This includes a detailed analysis of the side-channel properties of the different implementations.

 Start of Thesis: Anytime


References:

[1] M. Blott, T. B. Preußer, N. J. Fraser, G. Gambardella, K. O’brien, Y. Umuroglu, M. Leeser, and K. Vissers, “Finn-r: An end-to-end deep-learning framework for fast exploration of quantized neural networks,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 11, no. 3, pp. 1–23, 2018.
[2] Y. Umuroglu and M. Jahre, “Streamlined deployment for quantized neural networks,” arXiv preprint arXiv:1709.04060, 2017.
[3] L. Batina, S. Bhasin, D. Jap, and S. Picek, “{CSI}{NN}: Reverse engineering of neural network architectures through electromagnetic side channel,” in 28th {USENIX} Security Symposium ({USENIX} Security 19), pp. 515–532, 2019.
[4] A. Dubey, R. Cammarota, and A. Aysu, “Bomanet: Boolean masking of an entire neural network," arXiv preprint arXiv:2006.09532, 2020.

Prerequisites

  • VHDL/Verilog Knowledge
  • Sichere Implementierung Kryptographischer Verfahren (SIKA)
  • Python Skills

Contact

manuel.brosch@tum.de or matthias.probst@tum.de

Supervisor:

Matthias Probst, Manuel Brosch

Research Internships (Forschungspraxis)

SCA of AI Hardware Accelerator

Keywords:
SCA, Neural Networks, Hardware, FPGA

Description

Neural Networks are inevitable in everyday life. Speech and face recognition as well as driverless cars are just some examples where Artificial Neural Networks (ANN) are used. Training a deep ANN is very time-consuming and computational expensive. Thus, the intellectual property stored in an ANN is an asset worth to protect. Additionally, implementations on edge devices need to be power-efficient whilst maintaining a high throughput. [1] or [2] are examples for frameworks aiming to fulfill these requirements.


A side-channel attack can be used to extract the network parameters such as the number or type of layers, as well as weights and bias values. In [3, 4] side-channel attacks on different implementations of ANNs are performed. 

In this work, a side-channel attack on autogenerated implementations of different ANNs should be performed. This includes a detailed analysis of the side-channel properties of the different implementations.

 Start of Thesis: Anytime


References:

[1] M. Blott, T. B. Preußer, N. J. Fraser, G. Gambardella, K. O’brien, Y. Umuroglu, M. Leeser, and K. Vissers, “Finn-r: An end-to-end deep-learning framework for fast exploration of quantized neural networks,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 11, no. 3, pp. 1–23, 2018.
[2] Y. Umuroglu and M. Jahre, “Streamlined deployment for quantized neural networks,” arXiv preprint arXiv:1709.04060, 2017.
[3] L. Batina, S. Bhasin, D. Jap, and S. Picek, “{CSI}{NN}: Reverse engineering of neural network architectures through electromagnetic side channel,” in 28th {USENIX} Security Symposium ({USENIX} Security 19), pp. 515–532, 2019.
[4] A. Dubey, R. Cammarota, and A. Aysu, “Bomanet: Boolean masking of an entire neural network," arXiv preprint arXiv:2006.09532, 2020.

Prerequisites

  • VHDL/Verilog Knowledge
  • Sichere Implementierung Kryptographischer Verfahren (SIKA)
  • Python Skills

Contact

manuel.brosch@tum.de or matthias.probst@tum.de

Supervisor:

Matthias Probst, Manuel Brosch

Publications

2024

  • Probst, Matthias and Brosch, Manuel and Gruber, Michael and Sigl, Georg: DOMREP II. 2024 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2024Washington DC, USA more…
  • Schmidt, Patrick and Topko, Iuliia and Stammler, Matthias and Harbaum, Tanja and Becker, Juergen and Berner, Rico and Ahmed, Omar and Jagielski, Jakub and Seidler, Thomas and Abel, Markus and Kreutzer, Marius and Kirschner, Maximilian and Betancourt, Victor Pazmino and Sehm, Robin and Groth, Lukas and Neskovic, Andrija and Meyer, Rolf and Mulhem, Saleh and Berekovic, Mladen and Probst, Matthias and Brosch, Manuel and Sigl, Georg and Wild, Thomas and Ernst, Matthias and Herkersdorf, Andreas and Aigner, Florian and Hommes, Stefan and Lauer, Sebastian and Seidler, Maximilian and Raste, Thomas and Bozic, Gasper Skvarc and Ceberio, Ibai Irigoyen and Hassan, Muhammad and Mayer, Albrecht: EMDRIVE Architecture: Embedded Distributed Computing and Diagnostics from Sensor to Edge. 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024Valencia, Spain more…

2023

  • Brosch, Manuel and Probst, Matthias and Glaser, Matthias and Sigl, Georg: A Masked Hardware Accelerator for Feed-Forward Neural Networks With Fixed-Point Arithmetic. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023, 1-14 more…

2022

  • Brosch, Manuel and Probst, Matthias and Sigl, Georg: Counteract Side-Channel Analysis of Neural Networks by Shuffling. 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, 2022Antwerp, Belgium more…