Foto von Michaela Brunner

M.Sc. Michaela Brunner

Technische Universität München

Lehrstuhl für Sicherheit in der Informationstechnik (Prof. Sigl)

Dienstort

Lehrstuhl für Sicherheit in der Informationstechnik (Prof. Sigl)

Work:
Theresienstr. 90(0101)/1.ZG
80333 München

Raum: N1008ZG

Research Interests

  • Sequential netlist reverse engineering
  • Gate-level netlist analysis
  • Netlist obfuscation and locking methods

Teaching

Embedded Systems and Security WiSe 18/19, WiSe 19/20, SoSe 20, SoSe 21, SoSe 22

Open positions for students

If you are interested to be involved in one of my research topics as part of your Bachelor Thesis, Master Thesis or research internship, feel free to contact me. In addition to the topics below, also unsolicited applications are always welcome.

Research Internships (Forschungspraxis)

IP Risk Through Satisfiability Checking Tools

Description

Due to long production and supply chains, circuit designs are prone to theft and manipulation. Logic locking inserts a locking key into the circuit netlist to secure them against these risks. However, so called SAT-based attacks, which check the satisfiability of netlists, were developed to extract the locking keys again.

This work should create a better understanding of sequential SAT-based attacks and extend them towards further applications.

Please contact me to get more information about the topic and the aim of this work.

 

References:

  • Subramanyan, P.; Ray, S. & Malik, S. Evaluating the security of logic encryption algorithms 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2015, 137-143
  • El Massad, M.; Garg, S. & Tripunitara, M. Reverse engineering camouflaged sequential circuits without scan access 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017, 33-40

 

Contact

Michaela Brunner, M.Sc.

Technical University of Munich, Chair of Security in Information Technology

Room N1008, Email: michaela.brunner@tum.de

 

Supervisor:

Michaela Brunner

One Right Solution To Implement A State Machine?

Description

A finite state machine can be represented in several different ways. There is no one right solution. Designers make use of this fact to optimize power, area, or performance.

This work should first create a better understanding of what the limits of the representation of state machines are. Second, these findings should be interpreted in relation to various context.

Please contact me to get more information about the topic and the aim of this work.

 

 

References:

  • Hartmanis, J. Symbolic analysis of a decomposition of information processing machines Information and Control, Elsevier, 1960, 3, 154-178
  • Shelar, R. S.; Desai, M. P. & Narayanan, H. Decomposition of finite state machines for area, delay minimization Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No. 99CB37040), 1999, 620-625

 

 

Contact

Michaela Brunner, M.Sc.

Technical University of Munich, Chair of Security in Information Technology

Room N1008, Email: michaela.brunner@tum.de

Supervisor:

Michaela Brunner

Publications

2022

  • Brunner, Michaela and Hepp, Alexander and Baehr, Johanna and Sigl, Georg: Toward a Human-Readable State Machine Extraction. ACM Trans. Des. Autom. Electron. Syst. 27 (6), 2022 more… BibTeX

2021

  • Ludwig, Matthias and Hepp, Alexander and Brunner, Michaela and Baehr, Johanna: CRESS: Framework for Vulnerability Assessment of Attack Scenarios in Hardware Reverse Engineering. 2021 IEEE Physical Assurance and Inspection of Electronics (PAINE), 2021Washington DC, US more… BibTeX

2020

  • Brunner, M. and Gruber, M. and Tempelmeier, M. and Sigl, G.: Logic Locking Induced Fault Attacks. 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020Limassol, CYPRUS more… BibTeX
  • Zhang, G. L. and Li, B. and Li, M. and Yu, B. and Pan, D. Z. and Brunner, M. and Sigl, G. and Schlichtmann, U.: TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systemsde IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 2020, 1-1 more… BibTeX
  • Zhang, G. L. and Brunner, M. and Li, B. and Sigl, G.and Schlichtmann, U.: Timing Resilience for Efficient and Secure Circuits. 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 2020Beijing, China, 623-628 more… BibTeX

2019

  • Brunner, M. and Baehr, J. and Sigl, G.: Improving on State Register Identification in Sequential Hardware Reverse Engineering. 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2019Washington, D.C., USA more… BibTeX