Hardware Benchmarking and Hardware Implementations

In embedded devices and SoCs, cryptograhic primitives are frequently implemented as hardware accelerators. Such accelerators allow for low cost, low latency, low area, and high performance implementations of crypto systems.

To develop optimal designs, the complete system must be taken into account. This is the focus of our research group: we realize dedicated designs and benchmark cryptographic primitives.

Our current focus is on the CAESAR-competition. Also the emerging topic of leightweight cryptographic primitives is one of our research fields.


"CAESAR (Competition for Authenticated Encryption: Security, Applicability, and Robustness) will identify a portfolio of authenticated ciphers that (1) offer advantages over AES-GCM and (2) are suitable for widespread adoption. Cryptographic algorithm designers are invited to submit proposals of authenticated ciphers to CAESAR. All proposals will be made public for evaluation" Source

We are contributing to the evaluation process of the competition and published an open source benchmarking framework  to test CAESAR candidates on a ZYNQ-base FPGA platform in terms of functional correctness and power consumption.

We also publish the source code of our optimized implementations of CAESAR algorihtms for mutual testing.

Lab Course linked to our Research

Interested graduated students are encouraged to participate in our lab  to learn how to implement ciphers participating in the competitions. Excelent implementations get the chance to be published online, thus, directly contributing to the evalaution of the competition.

Selected Publications

M. Tempelmeier, J.-P. Kaps, and G.Sigl, "Experimental Power and Performance Evaluation of CAESAR Hardware Finalists", 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexiko, 2018

M. Tempelmeier, F. De Santis, G. Sigl and J. Kaps, "The CAESAR-API in the real world — Towards a fair evaluation of hardware CAESAR candidates," 2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington, DC, USA, 2018, pp. 73-80. doi:10.1109/HST.2018.8383893

Tempelmeier, Michael and De Santis, Fabrizio and Kaps, Jens-Peter and Sigl, Georg: An Area-Optimized Serial Implementation of ICEPOLE Authenticated Encryption Schemes. IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2016Washington D.C. Metropolitan Area, VA, USA