Floating-point units (FPUs) in commodity processors are optimized for speed but often exhibit subtle differences in timing and resource usage depending on the operands being processed (for example, when handling denormal numbers or overflows). These variations may be exploited by attackers through timing or microarchitectural side channels.

The goal of this project is to experimentally study floating-point behavior on x86 processors and evaluate whether information about processed data can be inferred from side-channel observations. Students will design and run microbenchmarks, collect timing and performance counter data, and analyze leakage patterns. The outcome is a better understanding of how floating-point hardware can expose unintended information channels and how such effects could impact security-sensitive applications.

• Survey known side channels in floating-point units
• Develop microbenchmarks to trigger and measure operand-dependent behavior
• Collect and analyze timing and performance data on Intel/AMD CPUs
• Evaluate potential leakage vectors and their severity
• (Summarize possible mitigations or design considerations)

Voraussetzungen

The student will study the fault attack surface of PQC signature implementations. Possible targets include:

• Randomness seeding: inducing reuse of sampling seeds across signatures

• Attempt counters: preventing incrementation, leading to repeated randomness

• Rejection checks: skipping norm or bounds checks, leaking biased outputs

Tasks include:

1. Literature review of fault attacks against lattice-based signatures

2. Identification of fault-sensitive components in reference implementations

3. Implementation of software-based fault models (e.g., instruction skip, register freeze)

4. Collection and analysis of faulty signatures to explore possible key recovery

Voraussetzungen

The student will analyze timing behavior of PQC signature algorithms and investigate potential side-channel leakage.

Possible directions include:

• Rejection sampling: measuring attempt counts and runtime variations.

• Coefficient bound checks: identifying early-exit patterns that depend on secret-derived values.

• Encoding steps: analyzing data-dependent runtime in signature encoding.

Tasks include:

1. Reviewing prior loop-abort timing attacks (e.g., on BLISS [1]).

2. Instrumenting PQC implementations to measure per-signature timing.

3. Collecting large datasets of timing traces under different inputs.

4. Applying statistical methods to correlate timing clusters with secret-dependent events. 

[1] Thomas Espitau, Pierre-Alain Fouque, Benoît Gérard, and Mehdi Tibouchi. 2017. Side-Channel Attacks on BLISS Lattice-Based Signatures: Exploiting Branch Tracing against strongSwan and Electromagnetic Emanations in Microcontrollers. In Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security (CCS '17). Association for Computing Machinery, New York, NY, USA, 1857–1874. https://doi.org/10.1145/3133956.3134028

Voraussetzungen

BIKE (Bit Flipping Key Encapsulation) is a post-quantum key exchange scheme based on quasi-cyclic moderate-density parity-check (QC-MDPC) codes. Security relies on the hardness of decoding random linear codes, where an attacker only knows the public matrix H, the syndrome s, and the exact weight of the error vector.

In this project the student will generate large datasets of BIKE ciphertexts and corresponding error vectors, and design experiments to analyze whether the weight (or distribution) of the error vector can be predicted directly from the syndrome and the parity-check matrix.

This includes:

• Implementing dataset generation with fixed public keys and varying error vectors

• Designing statistical or machine-learning based approaches to estimate error weights

• Evaluating how predictable the error structure is and whether such predictability could weaken BIKE’s assumed hardness

Voraussetzungen

Students interested in proposing their own research idea are welcome to do so within the broad areas of cryptography and security. Possible directions include Post-Quantum Cryptography, implementation security (e.g. side-channel and fault attacks, countermeasures), cryptographic system integration, and security at the system or network level.

Proposals should outline motivation, goals, relevant background, and a rough plan of the intended work. We will help refine and scope the idea to fit a seminar, bachelor thesis, IDP or FP.

In this seminar topic, the student will study the impact of quantum computing on blockchain technology and analyze the role of post-quantum cryptographic primitives in mitigating these threats. Based on the recommended paper “Blockchain in the Quantum Era: Surveying Security Challenges and Post-Quantum Cryptography” [1]  by Ramzan and Cimato, the student will investigate:

• The main vulnerabilities of current blockchain cryptographic components (signatures, hashing, consensus) against quantum algorithms such as Shor’s and Grover’s.

• The requirements and challenges of integrating PQC into blockchain infrastructures, with special attention to performance trade-offs (e.g., transaction size, throughput, decentralization).

• The implications for major platforms (Bitcoin, Ethereum, Monero, Zcash) and potential future designs for quantum-secure blockchains.

The student will summarize findings in a scientific article and presentation. Additional relevant literature beyond the provided paper should be included to build a well-founded perspective.

[1] Muhammad Taha Ramzan and Stelvio Cimato, Blockchain in the Quantum Era: Surveying Security Challenges and Post-Quantum Cryptography, in 2025 IEEE 49th Annual Computers, Software, and Applications Conference (COMPSAC), Toronto, ON, Canada, July 2025. https://ieeexplore.ieee.org/abstract/document/11126739