- Quantifying Compiler-induced Reliability Loss in Software-Implemented Hardware Fault Tolerance. 31st Asia and South Pacific Design Automation Conference (ASP-DAC), 2026 mehr… BibTeX Volltext (mediaTUM)
- Special Session – Hardware-Software Co-Design for Machine Learning Systems Made Open-Source. 2025 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2025 mehr… BibTeX
- Automated Graph-level Passes for TinyML Fault Tolerance. 2025 International Joint Conference on Neural Networks (IJCNN), IEEE, 2025, 1-9 mehr… BibTeX Volltext ( DOI ) Volltext (mediaTUM)
- Rapid Fault Injection Simulation by Hash-Based Differential Fault Effect Equivalence Checks. 2025 Design, Automation & Test in Europe Conference (DATE), 2025 mehr… BibTeX Volltext ( DOI ) Volltext (mediaTUM)
- XCP: An XCP-Proxy Server for Concurrent Multinode XCP Access. 2024 13th Mediterranean Conference on Embedded Computing (MECO), IEEE, 2024, 1-5 mehr… BibTeX Volltext ( DOI )
- Techniques and Tools for Fast Fault Injection Simulations of RISC-V Processors at RTL. RISC-V Summit Europe, 2024 mehr… BibTeX Volltext (mediaTUM) WWW
- Key-Recovery Fault Injection Attack on the Classic McEliece KEM. Code-Based Cryptography, Springer Nature Switzerland, 2023 mehr… BibTeX Volltext ( DOI ) WWW
- CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V. Proceedings of the 28th Asia and South Pacific Design Automation Conference (ASPDAC ), Association for Computing Machinery, 2023 mehr… BibTeX Volltext ( DOI ) WWW
- vRTLmod: An LLVM Based Open-Source Tool to Enable Fault Injection in Verilator RTL Simulations. Proceedings of the 20th ACM International Conference on Computing Frontiers (CF '23), Association for Computing Machinery, 2023 mehr… BibTeX Volltext ( DOI ) WWW
- Exploring the RISC-V Vector Extension for the Classic McEliece Post-Quantum Cryptosystem. 2021 22nd International Symposium on Quality Electronic Design (ISQED), IEEE, 2021 mehr… BibTeX Volltext ( DOI ) WWW
M.Sc. Johannes Geier
Technische Universität München
Lehrstuhl für Entwurfsautomatisierung (Prof. Schlichtmann)
Postadresse
Arcisstr. 21
80333 München
- Tel.: +49 (89) 289 - 23643
- Raum: 0509.04.912
- johannes.geier@tum.de