To cope with the increasing complexity of modern electronic systems, today's system designers rely heavily on the use of high-abstraction models of the targeted hardware system. A typical example of such a model are so-called Virtual Prototypes (VP). The abstraction level itself is loosely defined as the Electronic System Level (ESL).

ESL offers high simulation speed, and as such enables the exploration of different system architectures already during early stages of the design phase. However, detailed information about the system's timing performance is usually not provided. Especially for the design of embedded systems this depicts a major drawback, as these type of systems often need to meet strict real-time requirements. To solve this problem, several ESL simulators which consider the timing of the modelled hardware have been proposed in the literature. Tejas is one these simulators.

Main paper: Smruti Sarangi et al., "Tejas: A Java based Versatile Micro-Architectural Simulator", 2015

Ensuring contol flow integrity (CFI) by checking a control flow transfer follows an intended control flow graph (CFG) plays a crucial role in fault resilient computing systems. Different CFI schemes resemble techniques to counter both random faults due to environmental hazards or deliberate attacks.

In safety-critical systems, software-implemented hardware fault tolerance (SIHFT) methods help to harden off-the-shelf processing units against transient, and random soft errors and permanent hardware faults. After successful detection, processing system must respond and/or recover from these faults to ensure a safe state.

Optical networks-on-chips (ONoCs) have the advantages of high bandwidth, low power consumption, and low latency, so it is widely considered to have great research prospects in the field of multiprocessor systems. However, the scale of ONoCs is greatly limited by the power loss and optical signal-to-noise ratio (OSNR). Therefore, how to reduce the power loss of the routing paths and increase their OSNR has become an important research in the field of ONoCs. In this paper, on the basis of the structural characteristics of 2D mesh-based ONoCs, a general all-pass optical router model with five ports is proposed. According to this model, we propose a novel algorithm that can be used to find routing paths with the minimum power loss and improve the OSNR of the routing paths. The simulation results indicate that in the case of the longest optical link selection in different optical network scales, the optical routing paths selected by our algorithm are superior to the dimensional-order routing paths in terms of power loss and OSNR. Furthermore, our algorithm will obtain better performance with the expansion of network size.

With the breakthrough of silicon optical devices, optical network on chip has become a research hotspot. Optical logic circuit is the key unit that constitutes computing node in optical network on chip. Microring resonators (MRRs) are the basic components in optical logic circuits. However, due to the sensitivity of MRR to process drift and temperature, it is extremely prone to be faulty. Therefore, how to detect the optical logic circuit fault caused by MRRs is the key problem to improve its reliability. Firstly, the Binary Decision Diagram (BDD) of the fault-free and faulty circuit are established respectively; and then the BDD of the corresponding faulty circuit is constructed. The test BDD is obtained by XOR operation and simplification of the above two BDDs. The experimental results show the effectiveness of the proposed test generation based on BDD.

Deep learning is employed widely throughout various application domains. At Intel, one use case is the estimation of power, performance, and area (PPA) of embedded memories. While these models are in full productive use, gaining the trust of circuit designers is challenging because estimates may not always be accurate. Indicating the confidence (or, inversely, uncertainty) of predictions  is one way to address designers' concerns and build trust in deep learning models. In addition to building expert trust, uncertainty estimates may help to guide training data generation towards high-uncertainty areas.

Bayesian modeling has long been concerned with measures of uncertainty. In deep learning, on the other hand, gathering uncertainty estimates have been mostly ignored until recently. The goal of this project is to discuss and compare techniques available to measure uncertainty in regression neural networks.

• some knowledge of feed-forward neural networks / regression

One of the most common approaches in optimization is to make use of first and second derivatives, in order to find a minimum of a target function. In many cases though, this is not a viable option, as derivatives might not be available, or the function might not be differentiable at all.
For such problems, we need algorithms, that work without derivatives. This can be achieved for example using finite differences or interpolation.
One important algorithm family are the algorithms NEWUOA and BOBYQA by M. J. D. Powell.
The goal of this seminar is to gather works, that evaluate the performance of those algorithms. Furthermore, we want to create a performance matrix that puts Powell’s algorithms into relation with traditional algorithms over a range of different optimization problems.

Paper for BOBYQA (Has not to be read enirely!):
www.damtp.cam.ac.uk/user/na/NA_papers/NA2009_06.pdf

Knowledge in optimization and basic linear algebra is recommended.

Due to the complexity and nonlinearity of analog circuit design, design automation is still a challenging field. With the current progress in AI and its success in other areas, new possibilities arise for analog design. In this seminar the state of the art in AI for analog synthesis should be analyzed and a structured overview of different methods be developed.

Research paper to start with:

·      G. Wolfe and R. Vemuri, "Extraction and use of neural network models in automated synthesis of operational amplifiers," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 2, pp. 198-212, Feb. 2003, doi: 10.1109/TCAD.2002.806600.

https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1174095&isnumber=26375

Basic experience with artificial intelligence, analog design and optimization is recommended

Abstract— Antenna problem is a phenomenon of plasma induced gate oxide degradation. It directly affects manufacturability of VLSI circuits, especially in deep-submicron technology using high density plasma. Diode insertion is a very effective way to solve this problem Ideally diodes are inserted directly under the wires that violate antenna rules. But in today's high-density VLSI layouts, there is simply not enough room for "under-the-wire" diode insertion for all wires. Thus it is necessary to insert many diodes at legal "off-wire" locations and extend the antenna-rule violating wires to connect to their respective diodes. Previously only simple heuristic algorithms were available for this diode insertion and routing problem. In this paper we show that the diode insertion and routing problem for an arbitrary given number of routing layers can be optimally solved in polynomial time. Our algorithm guarantees to find a feasible diode insertion and routing solution whenever one exists. Moreover we can guarantee to find a feasible solution to minimize a cost function of the form /spl alpha/ /spl middot/ L + /spl beta/ /spl middot/ N where L is the total length of extension wires and N is the total number of Was on the extension wires. Experimental results show that our algorithm is very efficient.

Abstract— This paper presents a general multi-layer area router based on a novel grid construction scheme. The grid construction scheme produces more wiring tracks than the normal uniform grid scheme and accounts for differing design rules of the layers involved. Initial routing performed on the varying capacity grid is followed by a layer assignment stage. Routing completion is ensured by iterating local and global modifications in the layer assignment stage. Our router has been incorporated into the Custom Cell Synthesis project at MCC and has shown improved results for cell synthesis problems when compared with the router Mighty which was used in earlier versions of the project.

Abstract - Leakage currents are one major concern when designing recent CMOS devices, making design for leakage at all stages of the design process mandatory. Early leakage optimization requires early leakage prediction, and for electronic system level design, this means estimation capabilities at register transfer (RT) level or above. Existing models are very accurate, but slow [transistor level such as Berkeley Simulator (BSIM)], or the slightly faster gate level models (such as the Liberty library), disregard relevant parameters.

RT level leakage macro models are presented, which are faster than recent gate level models, while preserving the accuracy of the transistor level models to a great extent. An estimation framework is proposed, describing the subthreshold, gate, and junction leakage of recent technology devices. The models are characterized using BSIM compact models and a Monte Carlo process variation description. Each varying BSIM parameter can be described. As an example of use, channel length, oxide thickness, and channel doping are regarded together with the temperature, supply voltage and body voltage. The final macro model needs less than a hundred parameters to capture the leakage behavior of an entire RT component and is still analytically describing the dependence to the process parameters. Compared to SPICE + BSIM, a model prediction is computed up to a hundred times faster for large RT components, and is, depending on the analyzed technology, within 2.1% (for 16-nm LP)-6.8% (for 65-nm bulk) deviation over a wide range of operating conditions and process variation settings.

HELMS, Domenik, et al. Leakage models for high-level power estimation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, 37. Jg., Nr. 8, S. 1627-1639.

Because of the increasing dominance of interconnect issues in advanced IC technology, placement has become a critical step in the IC design flow. To get accurate interconnect information during the placement process, it is desirable to incorporate global routing into it. However, previous global routers are computationally expensive. It is impractical to perform global routing repeatedly during placement.

In this paper, we present an extremely fast and high-quality global router called FastRoute. In traditional global routing approaches, congestion is not considered during Steiner tree construction. So they have to rely on the time-consuming maze routing technique to eliminate routing congestion. Different from traditional approaches, we proposed a congestion-driven Steiner tree topology generation technique and an edge shifting technique to determine the good Steiner tree topologies and Steiner node positions. Based on the congestion-driven Steiner trees, we only need to apply maze routing to a small percentage of the two-pin nets once to obtain high quality global routing solutions. We also proposed a new cost function based on logistic function to direct the maze routing.

loorplanning is an important problem in very largescale integrated-circuit (VLSI) design automation as it determinesthe performance, size, yield, and reliability of VLSI chips. Fromthe computational point of view, VLSI floorplanning is an NP-hardproblem. In this paper, a memetic algorithm (MA) for a nonslicingand hard-module VLSI floorplanning problem is presented. ThisMA is a hybrid genetic algorithm that uses an effective geneticsearch method to explore the search space and an efficient localsearch method to exploit information in the search region. Theexploration and exploitation are balanced by a novel bias searchstrategy. The MA has been implemented and tested on popularbenchmark problems. Experimental results show that the MA canquickly produce optimal or nearly optimal solutions for all thetested benchmark problems.