For developing optimization strategies within the digital Electronic Design Automation (EDA) flow, Reinforcement Learning (RL) has been applied.  RL has been used for cell layout, placement, routing, etc. [1]. In particular, RL has been used in logic synthesis [2-3]. PrefixRL[2] is a deep RL framework for designing parallel prefix adders with optimal delay and area costs. DRiLLS [3] maps the design space exploration in the logic synthesis stage to a game environment.

This seminar topic should cover literature research on RL applications to logic synthesis. The student should explain in detail how the RL agent is built, its state/action space, and the reward function. Moreover, some results, advantages, and disadvantages should be analyzed.

References:

[1] Ren, Haoxing, et al. "Optimizing VLSI Implementation with Reinforcement Learning-ICCAD Special Session Paper." 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD). IEEE, 2021.

[2] R. Roy et al., "PrefixRL: Optimization of Parallel Prefix Circuits using Deep Reinforcement Learning," 2021 58th ACM/IEEE Design Automation Conference (DAC), 2021, pp. 853-858, doi: 10.1109/DAC18074.2021.9586094.

[3] A. Hosny, S. Hashemi, M. Shalan and S. Reda, "DRiLLS: Deep Reinforcement Learning for Logic Synthesis," 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 2020, pp. 581-586, doi: 10.1109/ASP-DAC47756.2020.9045559.

In recent years neural networks emerged as a promising solution to problems in various fields, ranging from life-style to industry.
Since neural networks are very compute-intensive, specialized hardware accelerators have been developed to improve their execution performance regarding latency and power consumption.
Although these hardware accelerators are already a significant step forward, neural networks tend to grow larger, putting more pressure on the hardware to cope with the larger models.
On top of that, certain safety-critical applications require very tight timing constraints to be met.
This development sparked intense research to further optimize the execution performance of neural network accelerators.
As part of this research, hardware-/software codesign approaches promise significant improvements by taking a holistic view on the system stack.
The aim of this topic is to evaluate and contrast different hardware-/software codesign approaches regarding their methodology, effectiveness, applicability and limitations.
To limit the scope of this topic, only techniques which target digital accelerators are to be considered.

Exploring the scheduling methods used when deploying multiple
inference graphs/tasks onto a single, ideally heterogeneous, platform

Modern design approaches for embedded systems rely heavily on abstract models of the targeted hardware, to allow early and fast simulations of the system. Typical examples of such models are Virtual Prototypes (VPs) and Instruction Set Simulators (ISSs).

While VPs and ISSs offer high simulation speeds, they are not capable of providing reliable information regarding the systems performance (i.e. its timing behavior). Cycle Accurate Simulators (CAS) are capable of providing more accurate data on the systems performance, but at the cost of reduced simulation speeds.

The ComCAS simulator explores the use of "compiled simulation" to increase the simulation speed of a CAS.

Electronic Design Automation (EDA) has enabled rapid speedup in the development of new electronic systems and devices. By means of hierarchical design paradigms, logic synthesis or floorplanning algorithms and timing analysis, etc. the time to market for new designs can be reduced, while the system complexity increases. However, most intellectual property in this domain is protected by major vendors. But recently, the attention on open-source projects in EDA has grown. For example, with OpenRoad [1], a RTL-to-GDSII design flow is under developement to make ASIC digital design process more accessible.

The goal of this topic should be a survey on current work in open-source tools for EDA. Major projects should be identified and its benefits and limitations should be investigated.

[1] KAHNG, Andrew B.; SPYROU, Tom. The OpenROAD project: Unleashing hardware innovation. In: Proc. GOMAC. 2021.

With the breakthrough of silicon optical devices, optical network on chip has become a research hotspot. Optical logic circuit is the key unit that constitutes computing node in optical network on chip. Microring resonators (MRRs) are the basic components in optical logic circuits. However, due to the sensitivity of MRR to process drift and temperature, it is extremely prone to be faulty. Therefore, how to detect the optical logic circuit fault caused by MRRs is the key problem to improve its reliability. Firstly, the Binary Decision Diagram (BDD) of the fault-free and faulty circuit are established respectively; and then the BDD of the corresponding faulty circuit is constructed. The test BDD is obtained by XOR operation and simplification of the above two BDDs. The experimental results show the effectiveness of the proposed test generation based on BDD.

One of the most common approaches in optimization is to make use of first and second derivatives, in order to find a minimum of a target function. In many cases though, this is not a viable option, as derivatives might not be available, or the function might not be differentiable at all.
For such problems, we need algorithms, that work without derivatives. This can be achieved for example using finite differences or interpolation.
One important algorithm family are the algorithms NEWUOA and BOBYQA by M. J. D. Powell.
The goal of this seminar is to gather works, that evaluate the performance of those algorithms. Furthermore, we want to create a performance matrix that puts Powell’s algorithms into relation with traditional algorithms over a range of different optimization problems.

Paper for BOBYQA (Has not to be read enirely!):
www.damtp.cam.ac.uk/user/na/NA_papers/NA2009_06.pdf

Knowledge in optimization and basic linear algebra is recommended.

Abstract— Antenna problem is a phenomenon of plasma induced gate oxide degradation. It directly affects manufacturability of VLSI circuits, especially in deep-submicron technology using high density plasma. Diode insertion is a very effective way to solve this problem Ideally diodes are inserted directly under the wires that violate antenna rules. But in today's high-density VLSI layouts, there is simply not enough room for "under-the-wire" diode insertion for all wires. Thus it is necessary to insert many diodes at legal "off-wire" locations and extend the antenna-rule violating wires to connect to their respective diodes. Previously only simple heuristic algorithms were available for this diode insertion and routing problem. In this paper we show that the diode insertion and routing problem for an arbitrary given number of routing layers can be optimally solved in polynomial time. Our algorithm guarantees to find a feasible diode insertion and routing solution whenever one exists. Moreover we can guarantee to find a feasible solution to minimize a cost function of the form /spl alpha/ /spl middot/ L + /spl beta/ /spl middot/ N where L is the total length of extension wires and N is the total number of Was on the extension wires. Experimental results show that our algorithm is very efficient.

Abstract— This paper presents a general multi-layer area router based on a novel grid construction scheme. The grid construction scheme produces more wiring tracks than the normal uniform grid scheme and accounts for differing design rules of the layers involved. Initial routing performed on the varying capacity grid is followed by a layer assignment stage. Routing completion is ensured by iterating local and global modifications in the layer assignment stage. Our router has been incorporated into the Custom Cell Synthesis project at MCC and has shown improved results for cell synthesis problems when compared with the router Mighty which was used in earlier versions of the project.

There is a global unmet need for rapid and cost-effective prognostic and diagnostic tools that can be used at the bedside or in the doctor’s office to reduce the impact of serious disease. Many cancers are diagnosed late, leading to costly treatment and reduced life expectancy. With prostate cancer, the absence of a reliable test has inhibited the adoption of screening programs. We report a microelectronic point-of-care metabolite biomarker measurement platform and use it for prostate cancer detection. The platform, using an array of photodetectors configured to operate with targeted, multiplexed, colorimetric assays confined in monolithically integrated passive microfluidic channels, completes a combined assay of 4 metabolites in a drop of human plasma in under 2 min. A preliminary clinical study using L-amino acids, glutamate, choline, and sarcosine was used to train a cross-validated random forest algorithm. The system demonstrated sensitivity to prostate cancer of 94% with a specificity of 70% and an area under the curve of 0.78. The technology can implement many similar assay panels and hence has the potential to revolutionize low-cost, rapid, point-of-care testing.

Dot and ripple nanopatterns on Si surfaces with defined symmetry and characteristic dot spacings of 50–70 nm were created by 1 keV Ar ion irradiation at normal incidence and simultaneous co-deposition of Fe atoms at grazing incidence. Fe was continuously supplied from different sputter targets surrounding the Si substrate, leading to a steady-state Fe content in the near-surface region of the substrates. The pattern formation is self-organized, most probably caused by ion-induced phase separation. Patterns were analyzed with atomic force microscopy and the Fe content in the irradiated layer was measured with Rutherford backscattering. The symmetries of the produced patterns are isotropic, four-fold symmetric, three-fold symmetric and various types of two-fold symmetric patterns, depending on the geometrical arrangement of the sputter targets. Pattern formation was studied for a steady-state coverage of Fe between 0.5 and 3.3 × 1015 Fe cm−2. The threshold coverage for the onset of pattern formation is about 0.5–1 × 1015 Fe cm−2. The coherence length of the patterns is comparable to the average dot spacing. Nevertheless, the autocorrelation analysis reveals a residual long-range periodicity of some patterns. The dot spacing can be adjusted between about 20 nm and several hundred nm depending on the ion species and ion energy.

Because of the increasing dominance of interconnect issues in advanced IC technology, placement has become a critical step in the IC design flow. To get accurate interconnect information during the placement process, it is desirable to incorporate global routing into it. However, previous global routers are computationally expensive. It is impractical to perform global routing repeatedly during placement.

In this paper, we present an extremely fast and high-quality global router called FastRoute. In traditional global routing approaches, congestion is not considered during Steiner tree construction. So they have to rely on the time-consuming maze routing technique to eliminate routing congestion. Different from traditional approaches, we proposed a congestion-driven Steiner tree topology generation technique and an edge shifting technique to determine the good Steiner tree topologies and Steiner node positions. Based on the congestion-driven Steiner trees, we only need to apply maze routing to a small percentage of the two-pin nets once to obtain high quality global routing solutions. We also proposed a new cost function based on logistic function to direct the maze routing.

loorplanning is an important problem in very largescale integrated-circuit (VLSI) design automation as it determinesthe performance, size, yield, and reliability of VLSI chips. Fromthe computational point of view, VLSI floorplanning is an NP-hardproblem. In this paper, a memetic algorithm (MA) for a nonslicingand hard-module VLSI floorplanning problem is presented. ThisMA is a hybrid genetic algorithm that uses an effective geneticsearch method to explore the search space and an efficient localsearch method to exploit information in the search region. Theexploration and exploitation are balanced by a novel bias searchstrategy. The MA has been implemented and tested on popularbenchmark problems. Experimental results show that the MA canquickly produce optimal or nearly optimal solutions for all thetested benchmark problems.