Manufacturing testing is a critical and costly step in semiconductor production. Every chip must be tested after fabrication to ensure it meets specifications before reaching the market. As chips become more complex, the cost and time of manufacturing testing grows significantly - making it one of the biggest cost drivers in semiconductor production. Machine Learning (ML) offers promising solutions to tackle these challenges. This seminar investigates the real and practical applications of ML in two key areas of semiconductor manufacturing testing:

1) Test Cost Reduction:

• How can ML reduce test time on Automatic Test Equipment (ATE)?
• Can ML predict which chips are likely to fail, enabling adaptive testing strategies? What are real industrial success stories in reducing test cost using ML?

2) Fault Detection and Diagnosis:

• How can ML improve defect detection accuracy during wafer probe and final test?
• Can ML help locate faults faster and more accurately than traditional methods?
• What are the current limitations of ML based fault diagnosis?

Students are expected to go beyond summarizing and critically evaluate where ML has truly delivered in manufacturing testing and where open challenges remain.

Recommended Starting Points:

• L. Sun et al., "Machine Learning Technologies for Semiconductor Manufacturing," 2024 Conference of Science and Technology for Integrated Circuits (CSTIC), Shanghai, China, 2024, pp. 1-7, doi: 10.1109/CSTIC61820.2024.10532076.
• S. Khan and P. Sarkar, "A Comprehensive Review of Machine Learning Applications in VLSI Testing: Unveiling the Future of Semiconductor Manufacturing," 2023 7th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), Kolkata, India, 2023, pp. 1-5, doi: 10.1109/IEMENTech60402.2023.10423398.
• Y. -L. Chen et al., "Exploring Machine Learning for Semiconductor Process Optimization: A Systematic Review," in IEEE Transactions on Artificial Intelligence, vol. 5, no. 12, pp. 5969-5989, Dec. 2024, doi: 10.1109/TAI.2024.3429479. S. Majumdar, U. Mallappa and H. Mostafa, "AI Alone isn't Ready for Chip Design: A Combination of Classical Search and Machine Learning May be the Way Forward," in IEEE Spectrum, vol. 61, no. 12, pp. 38-43, December 2024, doi: 10.1109/MSPEC.2024.10779342.

Modern automotive systems increasingly rely on Artificial Intelligence (AI) and Machine Learning (ML) for safety-critical functions such as autonomous driving and Advanced Driver Assistance Systems (ADAS). However, the established functional safety standard ISO 26262 was originally designed for deterministic hardware and software systems - not for AI based components. This raises a fundamental question: How can we certify and assign ASIL levels to AI-based safety critical systems? This seminar investigates the gap between current safety standards and AI-based systems, covering:

• The core problem: Why ISO 26262 struggles to accommodate the non-deterministic nature of AI and ML components.
• Emerging standards: How ISO/PAS 8800 and ISO 21448 (SOTIF) attempt to address AI safety requirements in automotive systems.
• New concepts: The proposed AI Safety Integrity Level frameworks and their relationship to traditional ASIL classification.
• Industry practice: How companies are currently attempting to achieve ASIL-D certification for AI-based systems.
• Open gaps: What remains unresolved even in the newest standards.

Students are expected to critically evaluate whether current and emerging standards are sufficient to guarantee the safety of AI systems in automotive applications and identify where future work is needed.

Recommended Starting Points:

• P. Iyenghar, E. Gracic and G. Pawelke, "A Systematic Approach to Enhancing ISO 26262 With Machine Learning-Specific Life Cycle Phases and Testing Methods," in IEEE Access, vol. 12, pp. 179600-179627, 2024, doi: 10.1109/ACCESS.2024.3506333.
• V. Vyas and Z. Xu, "Key Safety Design Overview in AI-driven Autonomous and Battery-electric Vehicles," 2024 2nd International Conference on Advancements and Key Challenges in Green Energy and Computing (AKGEC), Ghaziabad, India, 2024, pp. 1-8, doi: 10.1109/AKGEC62572.2024.10868556.
• M. A. Gosavi, B. B. Rhoades and J. M. Conrad, "Application of Functional Safety in Autonomous Vehicles Using ISO 26262 Standard: A Survey," SoutheastCon 2018, St. Petersburg, FL, USA, 2018, pp. 1-6, doi: 10.1109/SECON.2018.8479057.
• M. Gharib, P. Lollini, M. Botta, E. Amparore, S. Donatelli and A. Bondavalli, "On the Safety of Automotive Systems Incorporating Machine Learning Based Components: A Position Paper," 2018 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), Luxembourg, Luxembourg, 2018, pp. 271-274, doi: 10.1109/DSN-W.2018.00074.

Modern embedded systems require precise, verifiable behavioral models during hardware and software development. Petri nets, a formalism for modeling concurrent, distributed, and reactive systems, naturally specify and analyze the complex workflows of embedded systems. By capturing parallelism, synchronization, and resource dependencies, they enable engineers to reason formally about correctness early on.

Recent research has explored transforming Workflow Nets, a special form of Petri net, into more structured representations. The work in [1] introduces a formal notation for capturing workflows in a structured partially ordered workflow notation, providing a rigorous theoretical foundation for such transformations. Complementing this, the work presented in [2] proposes a practical algorithmic approach to bridging the gap between workflow nets and this notation, examining how workflow semantics can be preserved throughout the transformation. Together, both papers offer a comprehensive perspective on bridging the gap between expressive Petri net models and structured workflow formalisms.

This seminar focuses on methods for rewriting special Petri nets into partially ordered workflows. Participants will critically analyze the literature to understand core theories and algorithms driving these transformations. Emphasis will be placed on how structured workflow models directly support the development, verification, and analysis of modern embedded hardware and software systems. 

Bibliography

[1] Kourani, H., van Zelst, S.J. (2023). POWL: Partially Ordered Workflow Language. In: Business Process Management. BPM 2023. Lecture Notes in Computer Science, vol 14159. Springer, Cham. https://doi.org/10.1007/978-3-031-41620-0_6.
https://link.springer.com/chapter/10.1007/978-3-031-41620-0_6

[2] Kourani, H., Park, G., van der Aalst, W.M.P. (2025). Translating Workflow Nets into the Partially Ordered Workflow Language. In: Application and Theory of Petri Nets and Concurrency. PETRI NETS 2025. Lecture Notes in Computer Science, vol 15714. Springer, Cham. https://doi.org/10.1007/978-3-031-94634-9_12
https://link.springer.com/chapter/10.1007/978-3-031-94634-9_12

This seminar investigates the role of polyhedral techniques in modern machine learning compilers, with the goal of understanding which parts of the compilation pipeline—such as program analysis, scheduling, and code generation—are effectively handled using polyhedral models. The polyhedral framework provides a mathematical representation of loop nests and data dependencies, enabling powerful transformations and optimizations.

You will examine how and where polyhedral methods are applied in state-of-the-art ML compilers, and where alternative approaches are preferred. The seminar will critically assess the strengths and limitations of polyhedral techniques, particularly in the context of tensor computations, irregular workloads, and dynamic shapes, and identify which stages of the compilation process benefit most from their use.

This seminar explores post-training quantization (PTQ) methods tailored to Mamba models, a recent class of state space models designed for efficient sequence processing. Unlike transformer architectures, Mamba models exhibit different activation dynamics and parameter distributions, which can significantly impact quantization performance. The study will review existing PTQ approaches—such as uniform, non-uniform, static, and dynamic —and evaluate their applicability to Mamba architectures.

You will deliver an analysis of state-of-the-art methods, focusing on trade-offs between accuracy and runtime efficiency, including overheads from metadata storage, control flow, and memory access.

Recent advances in imaging technologies in domains such as medical imaging, remote sensing, and autonomous driving have led to the widespread availability of multi-megapixel images. However, training deep neural networks on such high-resolution data remains challenging due to severe GPU memory constraints and the rapidly increasing computational complexity of standard architectures [1]. Traditional convolutional neural networks (CNNs) [2] address this issue through patch-based processing or streaming techniques, enabling end-to-end learning on gigapixel-scale images. More recently, alternative architectures such as Vision Transformers [3] and hybrid CNN–Transformer models have been proposed, introducing new strategies such as multi-scale representations, sparse or local attention mechanisms, and hierarchical processing to efficiently capture both global and local context in large images.

The goal of this seminar is to survey deep learning approaches for high-resolution images, including CNNs, Transformer-based architectures, and emerging paradigms such as state-space models (VisionMamba [4]). The survey should cover key techniques for efficient high-resolution image processing, such as tiling and streaming, multi-resolution processing, efficient attention mechanisms, and hybrid architectures, in order to achieve a good trade-off between accuracy, GPU memory, and latency [1]. 

If this sounds interesting to you, please contact mikhael.djajapermana@tum.de

References and suggested starting reading list:

[1] Deep Learning for Efficient High-Resolution Image Processing. (Dede, Albert, et al., 2025) - Survey paper; relevant sections: 5.3., 5.4., and 6.

[2] Streaming Convolutional Neural Networks for End-to-End Learning With Multi-Megapixel Images. (Pinckaers, Hans, Bram Van Ginneken, and Geert Litjens et al., 2019)

[3] An image is worth 16x16 words: Transformers for image recognition at scale. (Dosovitskiy, Alexey, et al., 2020)

[4] Vision Mamba: Efficient Visual Representation Learning with Bidirectional State Space Model. (Zhu, Lianghui, et al., 2024)

Electronic Design Automation (EDA) spans widely from high-level system design to library cell characterization in IC design. For nearly all EDA applications, machine learning (ML) is currently under investigation.  However, as ML methods are progressing, e.g., from simple feed-forward neural networks to complex foundation models, the usage in EDA can also benefit from recent modeling approaches. A prominent obstacle for (simpler) data-driven ML models is their transferability from the circuits in the training set to unseen circuits. 

Here, (semi-)self-supervised methods could provide benefits, as a knowledge base of circuits in general is established and can be used for downstream tasks such as power, performance, and area prediction. Since circuits can be represented as graphs (e.g., at the netlist level), approaches such as masked graph autoencoders [1] could be reasonable. 

The goal of this seminar project is:

- Obtaining a concise overview of masked graph autoencoders

- Literature review on existing applications of masked graph autoencoders in EDA

- Outlook on potential applications for masked graph autoencoders

[1] Hou, Zhenyu, et al. "Graphmae: Self-supervised masked graph autoencoders." Proceedings of the 28th ACM SIGKDD conference on knowledge discovery and data mining. 2022.

A significant portion of DNN inference has shifted from cloud execution to edge execution due to concerns over data privacy and the constant need for connectivity to the cloud. Nevertheless, this presents its own challenges, since edge devices are resource-constrained. By using multiple distributed devices, good performance can be achieved. However, this necessitates the creation of novel scheduling and mapping approaches to coordinate the execution of tasks between devices. Within the scope of this topic, the student will familiarize themselves with the problem and learn about various mathematical formulations designed to optimally synchronize the execution of DNNs across multiple devices.

Voraussetzungen

The rapid progress of artificial intelligence (AI) has led to the emergence of a highly promising field known as neuro-symbolic (NeSy) computing. This approach combines the strengths of neural networks, which excel at data-driven learning, with the reasoning capabilities of symbolic AI. Neuro-symbolic models have the potential to overcome the limitations of each approach individually, resulting in interpretable and explainable AI systems that can reason over complex knowledge bases, learn from limited and/or noisy data, and be generalizable. However, the exploration of NeSy AI from a system perspective remains limited. This work targets an in-depth analysis of the state-of-the-art hardware-software co-design techniques for NeSy AI and discusses the associated challenges in improving system efficiency for heterogeneous computing.

Based on: X. Yang et al., "Neuro-Symbolic Computing: Advancements and Challenges in Hardware–Software Co-Design," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 3, pp. 1683-1689, March 2024, doi: 10.1109/TCSII.2023.3336251.