Memory safety bugs, e.g., buffer-over?ows or use-after-free, remain in the top ranks of security vulnerabilities. New hardware extensions such as the ARM Memory Tagging Extension help as mitigation, but are not yet available for all architectures. In this work, you will analyze and compare different methods to implement hardware-based memory safety approaches and their advantages/disadvantages. You will then implement hardware support for memory safety on RISC-V hardware.The work done in this thesis is part of the Chip Design Center Bayern Innovative that helps build an independent Chip Design infrastructure in Bavaria. In this project the Fraunhofer AISEC helps to develop secure RISC-V hardware and encourages publication of the ?nal results.

The following list of prerequisites is not complete, but shall give you an idea what is expected.

• Experience in a hardware description language like VHDL/Verilog
• Basic knowledge of computer architectures and embedded systems programming
• Basic knowledge in C/C++ to use our instrumentation and evaluation framework

Artificial Neural Networks (ANNs) are being deployed increasingly in safety-critical scenes, e.g., automotive systems and their platforms. Various fault tolerance/detection methods can be adopted to ensure the computation of the ML networks' inferences is reliable. A state-of-the-art solution is redundancy, where a computation is made multiple times, and their respective results are compared. This can be achieved sequentially or concurrently, e.g., through lock-stepped processors. However, this redundancy method introduces a significant overhead to the system: The required multiplicity of computational demand - execution time or processing nodes. To mitigate this overhead, several Algorithm-based Error Detection (ABED) approaches can be taken; among these, the following should be considered in this work:

1. Selective Hardening: Only the most vulnerable parts (layers) are duplicated.
2. Checksums: Redundancy for linear operations can be achieved with checksums. It aims to mitigate the overhead by introducing redundancy into the algorithms, e.g., filter and input checksums for convolutions [1] and fully connected (dense) layers [2].

The goals of this project are:

• Integrate an existing ABED-enhanced ML compiler for an industrial ANN deployment flow,
• design an experimental evaluation to test the performance impacts of 1. and 2. for an industry HW/SW setup, and
• conduct statistical fault injection experiments [3] to measure error mitigation of 1. and 2.

Related Work:
[1] S. K. S. Hari, M. B. Sullivan, T. Tsai, and S. W. Keckler, "Making Convolutions Resilient Via Algorithm-Based Error Detection Techniques," in IEEE Transactions on Dependable and Secure Computing, vol. 19, no. 4, pp. 2546-2558, 1 July-Aug. 2022, doi: 10.1109/TDSC.2021.3063083.
[2] Kuang-Hua Huang and J. A. Abraham, "Algorithm-Based Fault Tolerance for Matrix Operations," in IEEE Transactions on Computers, vol. C-33, no. 6, pp. 518-528, June 1984, doi: 10.1109/TC.1984.1676475.
[3] R. Leveugle, A. Calvez, P. Maistri, and P. Vanhauwaert, "Statistical fault injection: Quantified error and confidence," 2009 Design, Automation & Test in Europe Conference & Exhibition, Nice, France, 2009, pp. 502-506, doi: 10.1109/DATE.2009.5090716.

• Good understanding of Data Flow Graphs, Scheduling, etc.
• Good understanding of ANNs
• Good knowledge of Linux, (embedded) C/C++, Python
• Basic understanding of Compilers, preferably TVM and LLVM

This work will be conducted in cooperation with Infineon, Munich.

Analog circuit design heavily relies on the visualization of circuits via schematics, tables of measurements, and performance curves. In this work, we want to explore automatic image recognition techniques to classify available circuit information based on images. Additionally, we want to translate schematics into netlists and make graphs machine-readable.

First experience with computer vision recommended, i.e. lecture on machine learning, experience with pytorch, etc.

siehe pdf

The thesis will contribute to the research on Collage for integration of Deep Learning (DL) backends and provide insights into the challenges in this field. The strong demand for efficient and performant deployment of DL applications prompts the rapid development of a rich DL ecosystem. To keep up with this fast advancement, it is crucial for modern DL frameworks to efficiently integrate a variety of optimized tensor algebra libraries and runtimes as their backends and generate the fastest possible executable using these backends. However, current DL frameworks require significant manual effort and expertise to integrate every new backend while failing to unleash its full potential. Given the fast-evolving nature of the DL ecosystem, this manual approach often slows down continuous innovations across different layers; it prevents hardware vendors from the fast deployment of their cutting-edge libraries, DL framework developers must repeatedly adjust their hand-coded rules to accommodate new versions of libraries, and machine learning practitioners need to wait for the integration of new technologies and often encounter unsatisfactory performance. Collage is a DL framework that offers seamless integration of DL backends. Collage provides an expressive backend registration interface that allows users to precisely specify the capability of various backends. By leveraging the specifications of available backends, Collage automatically searches for an optimized backend placement strategy for a given workload and execution environment.

Your work:

1. Conduct a comprehensive literature review on Collage and similar frameworks
2. Conduct an experiment on Collage including a heterogenous system including UMA-integrated backends in TVM 

• Fundamental understanding of neural networks and embedded systems
• Basic understanding of TVM compiler
• Experience in programming C\C++ and Python
• Self-motivation and ability to work independently 

The thesis will contribute to the research on memory-centric approaches for the deployment of DNN models on resource-constraint heterogeneous systems and provide insights into the existing challenges in this field. In recent years, the rapid growth of Artificial Intelligence (AI) and the explosion of hardware devices with AI-specific features have led to a rising demand for tools and frameworks capable of translating Deep Learning models from high-level languages like Python into lower-level code optimized for a particular hardware target, often in C. This thesis focuses on edge heterogeneous systems with limited computational capabilities and low memory and prioritizes energy efficiency. The proliferation of diverse hardware platforms and programming ecosystems makes porting AI models to every device a non-trivial task. An ideal solution would be a universal tool that can translate high-level model representations, e.g., in Python, into low-level code while accommodating various hardware constraints, programming languages, and interfaces. Unfortunately, achieving this goal without compromising performance is still a challenge. For example, the TVM compiler stack is a popular open-source toolchain for deploying networks on many devices, including CPUs, GPUs, or ARM and RISC-V-based Microcontrollers (MCUs) but falls short when generating code for heterogeneous Systems-on-Chip (SoCs) containing different accelerators. Recent efforts have focused on integrating TVM with memory-oriented deployment frameworks like DORY [1] and ZigZag [2], aiming to address these challenges.

[1] Van Delm, et al. "HTVM: Efficient neural network deployment on heterogeneous TinyML platforms." In 2023 60th ACM/IEEE Design Automation Conference (DAC), pp. 1-6. IEEE, 2023.

[2] Hamdi, Mohamed Amine. "Integrating Design Space Exploration in Modern Compilation Toolchains for Deep Learning." PhD diss., Politecnico di Torino, 2023.

Your work:
1. Conduct a comprehensive literature review of existing works.
2. Compare the references to identify gaps and unresolved challenges. 3. Investigate the integration flow of references 1 and 2 in TVM.
4. Work on integrating the approaches outlined in references 1 and 2 using the UMA framework within TVM.  

Requirements:

• Fundamental understanding of neural networks and embedded systems
• Basic understanding of TVM compiler
• Experience in programming C\C++ and Python
• Self-motivation and ability to work independently 

M2-ISA-R is the code generation toolchain for the instruction set simulator ETISS, both developed by the Chair of Electronic Design Automation at TUM. The core of M2-ISA-R is a meta-model based modeling framework used to represent arbitrary instruction set architectures. Various parsers for architecture description languages and code generators for simulation models use these intermediate models.

The metamodel consists of structural and behavioral components. In this project, the goal is to research, apply and compare various simplification and optimization methods when preprocessing the behavioral syntax tree. A basic expression simplifier is already present, however it is very barebones and lacks required further AST simplification methods.

Depending on experience and individual expectations, the scope of the project can be variable for the chosen project type.

• Interest in learning about symbolic evaluation and simplification
• Ideally previous experience with static code analysis, natural language processing, compiler engineering etc.
• Very good knowledge of Python
• Some experience with parser generators, ideally ANTLR4

Analog circuit design, to this day, highly depends on expert knowledge. Similarly, efforts in analog design automation include the construction of databases of various sorts, such as analog building blocks, or entire netlists. Much of the necessary knowledge for cunstring such databases is either hidden within the analog designer’s mind, or by extension in published articles. With the recent success in language processing, an opportunity for automatic sighting and analysis of data arises. In this work, experiments with language models will be conducted, with the goal of building a database of articles treating a specific subject in analog design.

M2-ISA-R is the code generation toolchain for the instruction set simulator ETISS, both developed by the Chair of Electronic Design Automation at TUM. The core of M2-ISA-R is a meta-model based modeling framework used to represent arbitrary instruction set architectures. Various parsers for architecture description languages and code generators for simulation models use these intermediate models.

The metamodel consists of structural and behavioral components. In this project, the goal is to research, apply and compare various simplification and optimization methods when preprocessing the behavioral syntax tree. A basic expression simplifier is already present, however it is very barebones and lacks required further AST simplification methods.

Depending on experience and individual expectations, the scope of the project can be variable for the chosen project type.

• Interest in learning about symbolic evaluation and simplification
• Ideally previous experience with static code analysis, natural language processing, compiler engineering etc.
• Very good knowledge of Python
• Some experience with parser generators, ideally ANTLR4

Welcome to "Startup Microsystems: Innovate, Create, Compete – COSIMA Challenge," a dynamic and hands-on internship designed to empower students in harnessing their creativity and technical skills to participate in the COSIMA (Competition of Students in Microsystems Applications) contest. This internship is not just an academic pursuit; it's a journey towards becoming innovative entrepreneurs in the realm of sensor and microsystem applications.

COSIMA is a German national student competition. 

Overview:

In this practical internship, students will delve into the world of microsystems, exploring their components, functionalities, and potential applications. The focus will be on fostering creativity and teamwork as students work collaboratively to conceive, design, and prototype innovative solutions using sensors and microsystems.

Key Features:

Creative Exploration: Unlike traditional courses and internships, this one offers the freedom to choose and define your own technical challenge. Students will be encouraged to think outside the box, identify real-world problems, and propose solutions that leverage microsystems to enhance human-technology interactions.

Hands-On Prototyping: The heart of the internship lies in turning ideas into reality. Students will actively engage in the prototyping process, developing functional prototypes of their innovative concepts. Emphasis will be placed on understanding the practical aspects of sensor integration, actuation, and control electronics.

COSIMA Contest Preparation: The internship will align with the COSIMA competition requirements, preparing students to present their prototypes on the competition day. Guidance will be provided on creating impactful presentations that showcase the ingenuity and practicality of their solutions.

Go International: The winners of COSIMA will qualify to take part in the international iCAN competition. Guidance and preparation for the iCAN will be provided.

Entrepreneurial Mindset: Drawing inspiration from successful startups that emerged from COSIMA, the internship will instill an entrepreneurial mindset. Students will learn about the essentials of founding a startup, from business planning to pitching their ideas.

Us in the past:

iCANX Wettbewerb 2024 (cosima-mems.de)

Das war COSIMA 2023 (cosima-mems.de)

iCAN Wettbewerb 2023 (cosima-mems.de)

Sieger COSIMA 2022 (cosima-mems.de)

Intermediate German and English language proficiency is required.

Memory safety bugs, e.g., buffer-over?ows or use-after-free, remain in the top ranks of security vulnerabilities. New hardware extensions such as the ARM Memory Tagging Extension help as mitigation, but are not yet available for all architectures. In this work, you will analyze and compare different methods to implement hardware-based memory safety approaches and their advantages/disadvantages. You will then implement hardware support for memory safety on RISC-V hardware.The work done in this thesis is part of the Chip Design Center Bayern Innovative that helps build an independent Chip Design infrastructure in Bavaria. In this project the Fraunhofer AISEC helps to develop secure RISC-V hardware and encourages publication of the ?nal results.

The following list of prerequisites is not complete, but shall give you an idea what is expected.

• Experience in a hardware description language like VHDL/Verilog
• Basic knowledge of computer architectures and embedded systems programming
• Basic knowledge in C/C++ to use our instrumentation and evaluation framework

Artificial Neural Networks (ANNs) are being deployed increasingly in safety-critical scenes, e.g., automotive systems and their platforms. Various fault tolerance/detection methods can be adopted to ensure the computation of the ML networks' inferences is reliable. A state-of-the-art solution is redundancy, where a computation is made multiple times, and their respective results are compared. This can be achieved sequentially or concurrently, e.g., through lock-stepped processors. However, this redundancy method introduces a significant overhead to the system: The required multiplicity of computational demand - execution time or processing nodes. To mitigate this overhead, several Algorithm-based Error Detection (ABED) approaches can be taken; among these, the following should be considered in this work:

1. Selective Hardening: Only the most vulnerable parts (layers) are duplicated.
2. Checksums: Redundancy for linear operations can be achieved with checksums. It aims to mitigate the overhead by introducing redundancy into the algorithms, e.g., filter and input checksums for convolutions [1] and fully connected (dense) layers [2].

The goals of this project are:

• Integrate an existing ABED-enhanced ML compiler for an industrial ANN deployment flow,
• design an experimental evaluation to test the performance impacts of 1. and 2. for an industry HW/SW setup, and
• conduct statistical fault injection experiments [3] to measure error mitigation of 1. and 2.

Related Work:
[1] S. K. S. Hari, M. B. Sullivan, T. Tsai, and S. W. Keckler, "Making Convolutions Resilient Via Algorithm-Based Error Detection Techniques," in IEEE Transactions on Dependable and Secure Computing, vol. 19, no. 4, pp. 2546-2558, 1 July-Aug. 2022, doi: 10.1109/TDSC.2021.3063083.
[2] Kuang-Hua Huang and J. A. Abraham, "Algorithm-Based Fault Tolerance for Matrix Operations," in IEEE Transactions on Computers, vol. C-33, no. 6, pp. 518-528, June 1984, doi: 10.1109/TC.1984.1676475.
[3] R. Leveugle, A. Calvez, P. Maistri, and P. Vanhauwaert, "Statistical fault injection: Quantified error and confidence," 2009 Design, Automation & Test in Europe Conference & Exhibition, Nice, France, 2009, pp. 502-506, doi: 10.1109/DATE.2009.5090716.

• Good understanding of Data Flow Graphs, Scheduling, etc.
• Good understanding of ANNs
• Good knowledge of Linux, (embedded) C/C++, Python
• Basic understanding of Compilers, preferably TVM and LLVM

This work will be conducted in cooperation with Infineon, Munich.

M2-ISA-R is the code generation toolchain for the instruction set simulator ETISS, both developed by the Chair of Electronic Design Automation at TUM. The core of M2-ISA-R is a meta-model based modeling framework used to represent arbitrary instruction set architectures. Various parsers for architecture description languages and code generators for simulation models use these intermediate models.

The metamodel consists of structural and behavioral components. In this project, the goal is to research, apply and compare various simplification and optimization methods when preprocessing the behavioral syntax tree. A basic expression simplifier is already present, however it is very barebones and lacks required further AST simplification methods.

Depending on experience and individual expectations, the scope of the project can be variable for the chosen project type.

• Interest in learning about symbolic evaluation and simplification
• Ideally previous experience with static code analysis, natural language processing, compiler engineering etc.
• Very good knowledge of Python
• Some experience with parser generators, ideally ANTLR4

Welcome to "Startup Microsystems: Innovate, Create, Compete – COSIMA Challenge," a dynamic and hands-on internship designed to empower students in harnessing their creativity and technical skills to participate in the COSIMA (Competition of Students in Microsystems Applications) contest. This internship is not just an academic pursuit; it's a journey towards becoming innovative entrepreneurs in the realm of sensor and microsystem applications.

COSIMA is a German national student competition. 

Overview:

In this practical internship, students will delve into the world of microsystems, exploring their components, functionalities, and potential applications. The focus will be on fostering creativity and teamwork as students work collaboratively to conceive, design, and prototype innovative solutions using sensors and microsystems.

Key Features:

Creative Exploration: Unlike traditional courses and internships, this one offers the freedom to choose and define your own technical challenge. Students will be encouraged to think outside the box, identify real-world problems, and propose solutions that leverage microsystems to enhance human-technology interactions.

Hands-On Prototyping: The heart of the internship lies in turning ideas into reality. Students will actively engage in the prototyping process, developing functional prototypes of their innovative concepts. Emphasis will be placed on understanding the practical aspects of sensor integration, actuation, and control electronics.

COSIMA Contest Preparation: The internship will align with the COSIMA competition requirements, preparing students to present their prototypes on the competition day. Guidance will be provided on creating impactful presentations that showcase the ingenuity and practicality of their solutions.

Go International: The winners of COSIMA will qualify to take part in the international iCAN competition. Guidance and preparation for the iCAN will be provided.

Entrepreneurial Mindset: Drawing inspiration from successful startups that emerged from COSIMA, the internship will instill an entrepreneurial mindset. Students will learn about the essentials of founding a startup, from business planning to pitching their ideas.

Us in the past:

iCANX Wettbewerb 2024 (cosima-mems.de)

Das war COSIMA 2023 (cosima-mems.de)

iCAN Wettbewerb 2023 (cosima-mems.de)

Sieger COSIMA 2022 (cosima-mems.de)

Intermediate German and English language proficiency is required.

Welcome to "Startup Microsystems: Innovate, Create, Compete – COSIMA Challenge," a dynamic and hands-on internship designed to empower students in harnessing their creativity and technical skills to participate in the COSIMA (Competition of Students in Microsystems Applications) contest. This internship is not just an academic pursuit; it's a journey towards becoming innovative entrepreneurs in the realm of sensor and microsystem applications.

COSIMA is a German national student competition. 

Overview:

In this practical internship, students will delve into the world of microsystems, exploring their components, functionalities, and potential applications. The focus will be on fostering creativity and teamwork as students work collaboratively to conceive, design, and prototype innovative solutions using sensors and microsystems.

Key Features:

Creative Exploration: Unlike traditional courses and internships, this one offers the freedom to choose and define your own technical challenge. Students will be encouraged to think outside the box, identify real-world problems, and propose solutions that leverage microsystems to enhance human-technology interactions.

Hands-On Prototyping: The heart of the internship lies in turning ideas into reality. Students will actively engage in the prototyping process, developing functional prototypes of their innovative concepts. Emphasis will be placed on understanding the practical aspects of sensor integration, actuation, and control electronics.

COSIMA Contest Preparation: The internship will align with the COSIMA competition requirements, preparing students to present their prototypes on the competition day. Guidance will be provided on creating impactful presentations that showcase the ingenuity and practicality of their solutions.

Go International: The winners of COSIMA will qualify to take part in the international iCAN competition. Guidance and preparation for the iCAN will be provided.

Entrepreneurial Mindset: Drawing inspiration from successful startups that emerged from COSIMA, the internship will instill an entrepreneurial mindset. Students will learn about the essentials of founding a startup, from business planning to pitching their ideas.

Us in the past:

iCANX Wettbewerb 2024 (cosima-mems.de)

Das war COSIMA 2023 (cosima-mems.de)

iCAN Wettbewerb 2023 (cosima-mems.de)

Sieger COSIMA 2022 (cosima-mems.de)

Intermediate German and English language proficiency is required.

siehe pdf

siehe angehängtes pdf-File

M2-ISA-R is the code generation toolchain for the instruction set simulator ETISS, both developed by the Chair of Electronic Design Automation at TUM. The core of M2-ISA-R is a meta-model based modeling framework used to represent arbitrary instruction set architectures. Various parsers for architecture description languages and code generators for simulation models use these intermediate models.

The metamodel consists of structural and behavioral components. In this project, the goal is to research, apply and compare various simplification and optimization methods when preprocessing the behavioral syntax tree. A basic expression simplifier is already present, however it is very barebones and lacks required further AST simplification methods.

Depending on experience and individual expectations, the scope of the project can be variable for the chosen project type.

• Interest in learning about symbolic evaluation and simplification
• Ideally previous experience with static code analysis, natural language processing, compiler engineering etc.
• Very good knowledge of Python
• Some experience with parser generators, ideally ANTLR4