AI models keep growing faster than the devices that have to run them. The techniques that work at data-centre scale are exactly the ones unavailable on a battery-powered sensor node, a wearable, or a microcontroller, and a surprising number of published efficiency methods quietly assume otherwise. That mismatch leaves a great deal of untapped territory.

This open topic is aimed at students who want to go beyond a predefined project and explore their own research direction in efficient machine learning.

We are particularly interested in novel and creative approaches, including (but not limited to):

• Compression and quantization: new formats, new sensitivity criteria, or compression designed around what the target hardware can express
• On-device learning: adaptation, continual and federated learning under memory budgets measured in kilobytes
• Efficient architectures for constrained devices: compact transformers, state-space models, event-driven computation
• Hardware-software co-design: mapping, custom instructions, in-memory computing, or accelerator-aware algorithm design
• Benchmarking, measurement and tooling that makes efficiency claims verifiable rather than merely reported
• Completely new ideas that challenge existing assumptions

The goal is to develop a promising direction into a meaningful project, with the potential to grow into a thesis or a publication depending on the interest and the goal. We will help you refine and scope the idea.

Voraussetzungen

A model frozen at deployment slowly stops working. Sensors drift, users differ from the training population, devices are worn or mounted differently. Adapting on the device itself is the natural answer, but training is far more expensive than inference, and these devices have kilobytes of memory rathen than gigabytes.

The usual assumption is that fewer trainable parameters means less training memory. That comes from large language models, where optimizer state dominates, and it is wrong for embedded convolutional networks, where memory is dominated by the activations that automatic differentiation retains between the forward and backward pass. This difference opens more questions than it closes for edge training.

Depending on your interest and background, possible directions include (but are not limited to):

Memory-Efficient Adaptation

- Adapter and update designs whose backward pass provably never touches a full-width activation tensor

- Joint scheduling of freezing, recomputation and activation compression under a fixed byte budget, and what binds once saved activations are gone

Training Under Low-Precision Arithmetic

- Quantized backward passes, low-precision optimizer states and gradient quantization for devices without floating-point units

- Adapters that merge exactly on an integer backend, or fold into per-channel quantization scales rather than into the weight tensor

Learning Without Labels, and Continually

- Test-time adaptation, self-supervision on sensor streams and cross-sensor pseudo-labelling

- Stability on non-stationary streams, forgetting under kilobyte-scale replay buffers, and federated personalization across devices

Deployment, Measurement and Hardware Support

- Port memory-efficient training rules into an embedded runtime and measure real peak SRAM, latency and energy

- What hardware support would actually help on-device training, at the instruction, memory-hierarchy or dataflow level

Your Own Direction

- If you already have a question about training or adaptation on constrained devices that you want to pursue, bring it. A good idea from you is a better starting point than one from us

The work can lean toward algorithms, toward embedded systems and measurement, or toward co-design.

[1] H. Cai, C. Gan, L. Zhu, S. Han, “TinyTL: Reduce Memory, Not Parameters for Efficient On-Device Learning,” NeurIPS 2020. arXiv:2007.11622.

[2] J. Lin et al., “On-Device Training Under 256KB Memory,” NeurIPS 2022. arXiv:2206.15472.

[3] S. Patil et al., “POET: Training Neural Networks on Tiny Devices with Integrated Rematerialization and Paging,” ICML 2022. arXiv:2207.07697.

[4] E. J. Hu et al., “LoRA: Low-Rank Adaptation of Large Language Models,” ICLR 2022. arXiv:2106.09685.

[5] Y.-D. Kwon et al., “TinyTrain: Resource-Aware Task-Adaptive Sparse Training of DNNs at the Data-Scarce Edge,” ICML 2024. arXiv:2307.09988.

[6] D. Nadalini, M. Rusci, L. Benini, F. Conti, “Reduced precision floating-point optimization for DNN on-device learning on microcontrollers,” Future Generation Computer Systems 149 (2023) 212–226.

Voraussetzungen

Modern neural networks are far larger than the devices meant to run them, and quantization is what closes most of that gap. It is also the technique with the widest open research surface: what works for a convolutional network does not transfer to a transformer-based model, post-training methods break down in the low-bit regime, and the hardware the models must run on is changing underneath the algorithms.

Most of the field also optimizes proxies to understand quantization sensitivity under different bit precisions. Also most papers report model size, BitOps, or compression ratio, while what decides whether a model runs on a microcontroller is memory traffic, peak SRAM, and what the instruction set can actually express.

Recent research on precision allocation measures a layer's sensitivity based on various statistics such as the information flowing through the whole network rather than by a local property, Hessian information, Fisher information etc, which can be a working starting point, and a source of open questions.

Rather than prescribing a fixed path, we will scope a concrete contribution together, depending on your interests and background. Possible directions include (but are not limited to):

Quantization Algorithms

- Post-training quantization: calibration, outlier and rotation-based preprocessing, and the low-bit regime where post-training methods start to fail

- Quantization-aware training: gradient estimators, learned scales and clipping, and stability below four bits

Precision Allocation and Numeric Formats

- To answer which layers deserve which precision: sensitivity criteria compared under one common allocator, and allocation as an integer program under an explicit budget

- Block floating-point and microscaling formats (MXFP4, MXFP6, MXINT8, NVFP4), non-uniform grids, and quantization for analog compute-in-memory where a device noise floor caps how many bits are useful

Compression Beyond Quantization, and Beyond CNNs

- Structured and semi-structured pruning, low-rank factorization and distillation and whether stacked techniques compose or cancel

- Compact transformers and state-space models, where activations, KV cache and recurrent state, not weights, dominate the budget

Hardware-Aware Objectives and Co-Design

- Replace BitOps and size proxies with cost models fitted to real microcontroller and RISC-V measurements, and put them inside the search loop

- Co-optimize per-layer precision with dataflow and tiling, and explore custom RISC-V instructions for sub-byte kernels using the chair's compiler and simulator tooling

Your Own Direction

- If you already have a question in quantization or compression that you want to pursue, bring it. A good idea from you is a better starting point than one from us.

The work can lean toward algorithms and theory, toward systems and deployment, or toward hardware-software co-design. We aim to produce publishable research results, making this a good opportunity for students interested in academia or advanced R&D.

References

[1] Nagel, Markus et al. “A White Paper on Neural Network Quantization.” ArXiv abs/2106.08295 (2021)

[2] Gholami, Amir et al. “A Survey of Quantization Methods for Efficient Neural Network Inference.” ArXiv abs/2103.13630 (2021)

[3] Akbulut, Mehmet Emre et al. “InfoQ: Mixed-Precision Quantization via Global Information Flow.” AAAI 2026. ArXiv abs/2508.04753 (2026)

[4] Dong, Zhen et al. “HAWQ-V2: Hessian Aware trace-Weighted Quantization of Neural Networks.”, NeurIPS 2020. ArXiv abs/1911.03852 (2020)

[5] Frantar, Elias et al. “GPTQ: Accurate Post-Training Quantization for Generative Pre-trained Transformers.”, ICLR 2023. ArXiv abs/2210.17323 (2023)

[6] P. van Kempen et al., “MLonMCU: TinyML Benchmarking with Fast Retargeting,” CODAI 2023. arXiv:2306.08951.

Voraussetzungen

Modern deep neural networks (DNNs) require substantial memory for intermediate activations, which can become a major bottleneck when deploying models on memory-constrained edge devices and accelerators. Spatial or input tiling addresses this problem by dividing intermediate tensors into smaller regions that can be processed independently. Approaches such as Fused Depthwise Tiling (FDT) exploit this principle across multiple operators, reducing peak activation memory by avoiding the materialization of complete intermediate feature maps [1].

However, tiled execution introduces additional challenges. Convolutional operators require neighboring input elements around each output tile, resulting in overlapping halo regions. When tiling is propagated through longer operator chains, these regions can grow and introduce increasingly redundant computation and data movement. Choosing suitable tile sizes and deciding how far tiling should be propagated therefore creates a trade-off between peak memory consumption, redundant computation, and execution performance.

The IREE compiler provides an MLIR-based compilation infrastructure for deploying machine-learning workloads across heterogeneous hardware platforms [2]. Its existing support for tiling, fusion, and workload distribution provides a suitable foundation for implementing memory-oriented DNN tiling strategies. Furthermore, work such as TinyIREE demonstrates the relevance of IREE for resource-constrained DNN inference [3].

This project investigates the integration and evaluation of such tiling techniques within IREE. Possible directions include:

• Design and implementation of an MLIR/IREE compiler pass for spatial or input tiling of DNN operators

• Propagation of tiles across multiple operators to avoid materializing complete intermediate tensors

• Integration with existing IREE tiling, fusion, and lowering infrastructure

• Evaluation of peak memory usage, execution latency, and computational overhead

• Automated exploration of tile sizes and tiling/fusion strategies

• Investigation of strategies for mitigating increasing halo overhead across longer tiled operator chains

[1] Stahl, R., Mueller-Gritschneder, D., & Schlichtmann, U. (2023). Fused depthwise tiling for memory optimization in tinyml deep neural network inference. arXiv preprint arXiv:2303.17878.

[2] https://github.com/iree-org/iree

[3] Hsin-I Cindy Liu, Marius Brehler, Mahesh Ravishankar, Nicolas Vasilache, Ben Vanik, and Stella Laurenzo. 2022. TinyIREE: An ML Execution Environment for Embedded Systems From Compilation to Deployment. IEEE Micro 42, 5 (Sept.-Oct. 2022), 9–16. https://doi.org/10.1109/MM.2022.3178068 

Voraussetzungen

Modern DNN accelerators increasingly employ heterogeneous multi-core and chiplet-based architectures to meet the growing computational demands of deep learning. Besides distributing computation across multiple accelerator cores, these systems increasingly integrate multiple off-chip memory resources, such as HBM stacks, distributed DRAM controllers, or chiplet-local memories. Efficient placement of tensors across these memories is crucial for reducing communication overhead, balancing memory bandwidth, and improving overall inference performance. However, the Stream design space exploration framework currently assumes a single off-chip memory, limiting its applicability to emerging distributed memory architectures [1].

Memory placement has been extensively studied in related domains, including NUMA systems [2], heterogeneous memory architectures, and multi-chiplet GPUs [3], where locality-aware placement, bandwidth balancing, and memory migration are key optimization techniques. More recently, locality-aware tensor placement across multiple HBM stacks has been shown to significantly reduce remote memory accesses and improve execution efficiency in chiplet-based systems [4]. Similar challenges arise for DNN accelerators, where the placement of weights and activations directly impacts communication, memory utilization, and execution efficiency. Nevertheless, distributed off-chip memory placement for heterogeneous DNN accelerator architectures remains largely unexplored.

This project investigates off-chip memory placement strategies for heterogeneous DNN accelerators by extending the Stream DSE framework. Possible directions include:

• Extending Stream to support multiple distributed off-chip memories
• Investigation of memory placement strategies for weights and activations
• Static and heuristic-based tensor placement algorithms
• Analysis of communication, bandwidth, latency, and energy trade-offs
• Evaluation on heterogeneous and chiplet-based accelerator architectures

References

[1] A. Symons, L. Mei, S. Colleman, P. Houshmand, S. Karl and M. Verhelst, "Stream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators," IEEE Transactions on Computers, vol. 74, no. 1, pp. 237–249, Jan. 2025.

[2] D. Gureya et al., "Bandwidth-Aware Page Placement in NUMA," 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), New Orleans, LA, USA, 2020, pp. 546-556, doi: 10.1109/IPDPS47924.2020.00063.

[3] Park, J., Jang, S., Kwon, O., Lee, Y., & Hong, S. (2025, October). Leveraging Chiplet-Locality for Efficient Memory Mapping in Multi-Chip Module GPUs. In Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture (pp. 1040-1057).

[4] Chung, E., Ju, J. H., & Kim, H. (2026). Making Locality-aware GEMM Compatible with Page-Granularity Placement on Chiplet GPUs. arXiv preprint arXiv:2606.11718.

Voraussetzungen

Hardware-Aware Acceleration of Large-Scale MIQP Optimization for Future Chiplet Systems

Future chiplet-based systems require complex decisions about how workloads should be partitioned, mapped, and scheduled across multiple interconnected processing elements. At the chair, an optimization framework has been developed that formulates these decisions as a mixed-integer quadratic programming problem. The framework jointly considers objectives such as execution time, communication cost, energy consumption, and resource utilization.

Although modern GPUs provide substantial acceleration for many scientific and machine-learning workloads, their advantages are much more limited for mixed-integer optimization. State-of-the-art MIQP solvers are commonly based on branch-and-bound and related search procedures. These algorithms involve irregular control flow, dynamically evolving search trees, frequent synchronization, and memory-access patterns that are difficult to parallelize efficiently on conventional GPUs. As a result, solver performance often remains strongly dependent on CPU execution.

However, defining the “best CPU” for this workload is not straightforward. Solver performance may depend on many architectural properties, including single-thread performance, core count, cache capacity, memory bandwidth, memory latency, NUMA behavior, vector capabilities, and communication overhead between cores. At the same time, emerging computing platforms and specialized architectures may offer new opportunities for accelerating irregular optimization workloads.

In this research project, you will investigate how different hardware architectures affect the performance of large-scale MIQP-based scheduling and partitioning problems. The project will begin with a systematic benchmarking study across available computing platforms. Based on the observed bottlenecks, you will then develop and evaluate strategies that exploit the strengths of each architecture more effectively.

Possible research directions include:

• benchmarking CPUs with different core, cache, memory, and NUMA characteristics,
• analyzing solver behavior at the root relaxation and throughout the branch-and-bound tree,
• identifying which solver phases are limited by computation, memory access, synchronization, or search efficiency,
• evaluating many-core CPUs and heterogeneous computing platforms,
• investigating emerging architectures designed for irregular, graph-oriented, or combinatorial workloads,
• optimizing thread placement, memory allocation, solver parameters, and parallel search strategies,
• designing workload-aware strategies for selecting hardware and solver configurations,
• and exploring hybrid approaches in which selected solver components are offloaded to accelerators.

The project should go beyond reporting total runtime. Detailed profiling should be used to understand how hardware characteristics influence node processing speed, relaxation solving, cut generation, heuristic execution, memory consumption, synchronization overhead, and the evolution of primal and dual bounds.

A central goal is to determine whether different stages of the optimization process benefit from different hardware characteristics. This may enable adaptive strategies that select solver configurations dynamically, distribute work across heterogeneous resources, or assign specific subproblems to the architecture best suited to them.

Voraussetzungen

This project investigates automatic synthesis of multi-function RISC-V hardware accelerators for edge computing cores. It will extend uhLS [1], a compact, open-source High-level Hardware Synthesis (HLS) framework that lowers C code through intermediate representations into drivers, RTL, and ASIC-oriented flows, enabling the synthesis of several functions into a single shared accelerator block.

The goal is to synthesize multiple kernels, for example, DSP operations and AI inference primitives, into a single tightly coupled accelerator attached to a RISC-V processor pipeline. The main focus is on resource reuse across functions, especially shared multipliers, adders, memories, register files, and control logic, instead of generating one accelerator per function.

The thesis will extend the uhLS scheduling, binding, and backend flow to support multiple top-level functions, a shared datapath, and a dispatch/control mechanism. The generated accelerator should expose custom RISC-V instructions through a tightly coupled interface, with CV-X-IF/CORE-V-XIF [4] and SCAIE-V [5] as possible candidates, as they support external coprocessor-style instruction extensions without modifying the CPU RTL.

A second focus is synchronization. The project should compare statically timed accelerators, where latency is known to the compiler or to the issue logic, with explicit synchronization, such as ready/valid handshakes, status polling, or special synchronization instructions. The toolchain should reuse CoreDSL2 [2] for ISA/custom-instruction descriptions, and Seal5 [3] to generate LLVM [6]/compiler support for those custom instructions.

Related Work:

[1] µhLS / uhLS: Micro High-Level Synthesis Tool. https://github.com/JoGei/uhls

[2] CoreDSL2: ISA Description Language. Domain-specific language for modeling instruction-set architectures and custom ISA extensions; relevant as the architectural description layer for custom instructions.https://minres.github.io/CoreDSL/

[3] P. Van Kempen, M. Salmen, D. Mueller-Gritschneder, and U. Schlichtmann, "Seal5: Semi-Automated LLVM Support for RISC-V ISA Extensions Including Autovectorization," 2024 27th Euromicro Conference on Digital System Design (DSD), Paris, France, 2024, pp. 335-342, doi: 10.1109/DSD64264.2024.00052.

[4] OpenHW CORE-V-XIF / CV-X-IF Specification. Standardized RISC-V extension interface. https://docs.openhwgroup.org/projects/openhw-group-core-v-xif/en/latest/intro.html

[5] SCAIE-V. Open-source scalable interface for RISC-V ISA extensions.https://github.com/esa-tu-darmstadt/SCAIE-V-2.0

[6] Lattner, Chris, and Vikram Adve. "LLVM: A compilation framework for lifelong program analysis & transformation." International symposium on code generation and optimization, 2004. CGO 2004.. IEEE, 2004.

Voraussetzungen

Project Overview

Digital Microfluidics (DMF) is a cutting-edge technology that enables the precise manipulation of minute fluid volumes (droplets) via electrical actuation. We currently have a functional web-based design tool that allows researchers to create custom PCB-based and glass-based DMF chips. This platform streamlines the transition from concept to manufacturable hardware by providing features like custom electrode placement, automated routing, and experiment definition.

We are looking for motivated students to join our follow-up project. The goal is to extend the platform's functional modules and refine the core routing algorithms to handle increasingly complex chip architectures.

Tasks

As a student on this project, you will focus on two primary areas:

1. Platform Extension & Feature Enhancement

• Integrated Path Planning: Develop an automated droplet path planning feature where users can select start and end points, and the system generates the optimal movement sequence.
• Functional Module Libraries: Create templates and interfaces for specialized biological and chemical detection modules to improve design efficiency for specific experimental scenarios.
• Advanced UI/UX: Enhance the interactive editor, building upon existing features like "undo/redo," "copy/paste," and the "parallel electrode" batch processing system.

2. Routing Algorithm Refinement

• Algorithm Optimization: Work with our existing WebAssembly (WASM) and Web Worker-based routing engine to improve performance and success rates for high-density designs.
• Geometric Refinement: Modify the grid-based routing and collision detection logic to support finer electrode spacings and complex trace widths.
• Via Management: Refine the dynamic via cost mechanisms to optimize vertical interconnections between PCB layers.

Technical Environment

You will work with a modern, high-performance tech stack:

• Frontend: Vue 3, Element Plus, and SVG for vector graphics rendering.
• Core Logic: C++ (compiled to WebAssembly) for heavy computational tasks.
• Communication: Web Serial API for real-time hardware interfacing.
• Hardware Integration: Exporting KiCad-compatible files for physical PCB manufacturing.

Requirements

• Strong interest in Electronic Design Automation (EDA) or Microfluidics.
• Proficiency in JavaScript/TypeScript (preferably Vue 3) or C++.
• Basic understanding of geometric algorithms or PCB design is a plus.

Robust and Explainable Cas13d Guide RNA Design

RNA-targeting CRISPR systems such as Cas13d have emerged as powerful tools for programmable transcriptome engineering. While STOA frameworks improve practical guide RNA design using sequence-only deep learning models and interpretable interfaces, important challenges remain unresolved. Current systems primarily optimize predicted efficacy, while real-world applications require balancing multiple objectives including specificity, robustness across transcripts, structural accessibility, and uncertainty estimation.

This project aims to develop a next-generation design automation framework that performs multi-objective and uncertainty-aware guide RNA optimization for Cas13d systems. The student will investigate how deep learning architectures can jointly model guide efficacy, off-target risk, transcript accessibility, and confidence estimation using only computationally obtainable information.

The project may include:

• designing improved hybrid architectures (Transformer/CNN/attention-based models),
• integrating RNA secondary structure predictions or accessibility priors,
• developing uncertainty-aware ranking methods,
• implementing multi-objective scoring and candidate ranking,
• creating explainability methods for sequence-level interpretation,
• evaluating generalization across transcripts or datasets,
• and optionally extending the interactive natural-language explanation interface.

The final outcome should be a deployable prototype that produces ranked and interpretable guide RNA candidates from raw transcript sequences while improving robustness and transparency in practical CRISPR RNA-targeting workflows.

Possible Research Questions

• Can uncertainty estimation improve trustworthiness in guide RNA ranking?
• How can off-target risk and efficacy be jointly optimized?
• Which sequence motifs or contextual interactions most strongly determine Cas13d activity?
• Can RNA structure-aware representations improve prediction using only computational inputs?
• How transferable are learned guide design principles across datasets or organisms?

Voraussetzungen

The intersection of artificial intelligence and hardware/system design is rapidly evolving. Many traditional problems in areas such as chip design, optimization, and system architecture are being revisited with modern machine learning techniques—yet there is still vast untapped potential for new ideas.

This open topic is aimed at students who want to go beyond predefined projects and instead explore their own research direction. We are particularly interested in novel and creative approaches, including (but not limited to):

• Applying machine learning to classical hardware or EDA problems
• Reinforcement learning or optimization for system design and scheduling
• AI-driven design space exploration or co-design approaches
• Using modern paradigms such as foundation models or autonomous research/optimization agents
• Completely new ideas that challenge existing workflows or assumptions

The goal is to identify promising research directions and develop them into meaningful projects, with the potential to grow into a thesis or even a research publication.

You will work closely with supervision to refine your idea, scope the problem, and develop a concrete research plan—but the starting point should come from you.

Voraussetzungen

Modern chip design involves increasingly complex optimization problems, in which millions of interdependent design decisions must be made under strict physical and performance constraints. One central problem in this area is macro placement: arranging large components, such as SRAM blocks and intellectual property modules, on a chip while jointly optimizing routing congestion, timing, power delivery, wirelength, and area utilization.

Macro placement is inherently challenging. It combines a highly discrete and constrained search space with multiple competing objectives and strong global dependencies between placement decisions. Classical placement methods have been refined over decades and remain highly effective, but recent advances in machine learning and generative modeling offer promising opportunities to complement or improve existing approaches.

In this research internship, you will develop and evaluate novel methods for macro placement and related combinatorial optimization problems. The goal is to investigate algorithms that can scale to large, highly constrained systems while producing high-quality solutions within realistic runtime limits.

Possible research directions include:

• reinforcement learning and graph neural network approaches,
• generative methods such as diffusion models for producing or refining placements,
• hybrid methods combining machine learning with classical heuristics or mathematical optimization,
• learned search, ranking, or proposal mechanisms,
• scalable approximation and local-search techniques,
• and improvements to established placement algorithms using modern machine-learning and optimization tooling.

A particular emphasis may be placed on exploring how generative models can learn distributions over high-quality placements, incorporate physical and design-rule constraints, and guide downstream search or refinement procedures. Rather than replacing established optimization methods entirely, such models may serve as initialization mechanisms, proposal generators, surrogate models, or components within hybrid optimization pipelines.

The developed approaches will be evaluated on representative macro-placement benchmarks using relevant physical-design metrics, including wirelength, congestion, timing-related proxies, constraint satisfaction, solution quality, scalability, and runtime.

Voraussetzungen

Recent advances in AI/ML models (e.g., large language models) demand unprecedented compute and memory resources, making efficient system design a central challenge. New approaches, such as energy-aware co-optimization of hardware architectures and workload execution, enable significant improvements in energy-delay efficiency and scalability .

This thesis builds on such optimization-driven frameworks and opens up a range of possible research directions. Rather than prescribing a fixed path, the goal is to let you explore and define your own contribution within this space, depending on your interests.

Possible directions include (but are not limited to):

• Optimization & Algorithms
  • Improve scalability and efficiency of optimization solvers (e.g., MIQP-based approaches)
  • Develop approximation, heuristic, or hybrid optimization techniques
  • Explore alternative formulations for large-scale design space exploration
• AI for Systems / Learning-Based Methods
  • Investigate reinforcement learning or learning-based approaches for scheduling, mapping, or architecture design
  • Compare learned vs. analytical optimization strategies
• Scalable Systems & Workloads
  • Extend analyses to extremely large workloads (e.g., LLM-scale systems)
  • Study trade-offs between performance, energy, and hardware constraints
• Hardware & Architecture Exploration
  • Analyze emerging architectures such as multi-chiplet systems
  • Explore memory hierarchies, interconnects, and power management strategies
• Tooling & Visualization
  • Develop intuitive interfaces or visual analytics tools for design space exploration
  • Make complex optimization results interpretable and interactive

The work can be adapted toward a more theoretical, systems-oriented, or practical/software-driven thesis. We aim to produce publishable research results, making this an excellent opportunity for students interested in academia or advanced R&D.

Voraussetzungen

Power dissipation of integrated circuits (IC) is crucial, as it directly influences the battery life of edge devices, but also the cooling requirements for servers. To get to power-aware IC designs, precise power modeling is crucial in the design flow. Usually, this is done by a mapping of input features, like input signal activities or the number of gates in the design, to dynamic, static, or total power. Here, recently, machine learning (ML)-based models are in focus. 

The drawback of ML-based models is their limited transferability from circuit designs used in training to unseen circuits. Foundation models, like large language models, have shown great potential in other domains through their generalizability. Hence, they could also support here in the transferability problem of power modeling. Foundation models specifically designed for ICs, like the NetTAG [1], have been proposed. But, it is still open if these complex frameworks provide a significant benefit to power modeling.

The goal of this project is:

- Getting familiar with the NetTAG framework and its adapted version at the chair

- Design a downstream task for power estimation

- Evaluation of the transferability of NetTAG+downstream task

[1] Fang, Wenji, et al. "Nettag: A multimodal rtl-and-layout-aligned netlist foundation model via text-attributed graph." 2025 62nd ACM/IEEE Design Automation Conference (DAC). IEEE, 2025.

Voraussetzungen

Emerging computing architectures increasingly rely on chiplet-based systems and distributed execution to efficiently run complex workloads such as AI inference. In such systems, computations and intermediate results are exchanged between multiple processing units. Ensuring the integrity and correctness of these computations becomes an important challenge, particularly in the presence of hardware faults, communication errors, or malicious manipulation.

Techniques for detecting computational errors have long been studied, for example, through Algorithm-based Fault Tolerance (ABFT) methods for linear algebra operations [1]. More recently, similar concepts have been explored for machine learning workloads and NN inference, where protecting intermediate results and detecting corrupted computations is becoming increasingly important [2], [3], [4], [5]. At the same time, emerging architectures such as chiplet-based systems introduce new challenges for ensuring reliable execution across distributed compute units.

This student project investigates mechanisms for verifying the correctness of distributed AI computations in heterogeneous and chiplet-based architectures. Possible directions include:

• Techniques for integrity verification of distributed AI inference

• Detection of faults or corrupted intermediate results

• Lightweight verification mechanisms based on algorithmic or system-level approaches

• Analysis of trade-offs between reliability, performance, and overhead

References

[1] Kuang-Hua Huang and J. A. Abraham, "Algorithm-Based Fault Tolerance for Matrix Operations," in IEEE Transactions on Computers, vol. C-33, no. 6, pp. 518-528, June 1984, doi: 10.1109/TC.1984.1676475.

[2] S. K. S. Hari, M. B. Sullivan, T. Tsai and S. W. Keckler, "Making Convolutions Resilient Via Algorithm-Based Error Detection Techniques," in IEEE Transactions on Dependable and Secure Computing, vol. 19, no. 4, pp. 2546-2558, 1 July-Aug. 2022, doi: 10.1109/TDSC.2021.3063083.

[3] J. Hoefer, M. Stammler, F. Kreß, T. Hotfilter, T. Harbaum and J. Becker, "BayWatch: Leveraging Bayesian Neural Networks for Hardware Fault Tolerance and Monitoring," 2024 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Didcot, United Kingdom, 2024, pp. 1-6, doi: 10.1109/DFT63277.2024.10753546.

[4] Z. Chen, G. Li and K. Pattabiraman, "A Low-cost Fault Corrector for Deep Neural Networks through Range Restriction," in IEEE Design & Test, doi: 10.1109/MDAT.2025.3618758.

[5] J. Kappes, J. Geier, P. van Kempen, D. Mueller-Gritschneder and U. Schlichtmann, "Automated Graph-level Passes for TinyML Fault Tolerance," 2025 International Joint Conference on Neural Networks (IJCNN), Rome, Italy, 2025, pp. 1-9, doi: 10.1109/IJCNN64981.2025.11227379.

Voraussetzungen

Are you interested in hands-on experience in the emerging field of microfluidics? We are seeking a motivated student to join an innovative project focused on developing a PCB (Printed Circuit Board)-based digital microfluidics (DMF) platform. This project offers an excellent opportunity to apply your knowledge of hardware and PCB design while diving into the fascinating world of microfluidics.

About Digital Microfluidics (DMF):

Digital microfluidics (DMF) is a technology that allows precise manipulation of tiny droplets on a microscale using electrical fields. Unlike continuous-flow microfluidics, which relies on channels and pumps, DMF provides flexibility by enabling individual droplets to be moved, merged, split, or mixed on an open surface. This droplet-based control offers a powerful approach for various applications, from biomedical assays to chemical synthesis, with the benefit of reconfigurability and automation.

Project Scope:

In this project, you will focus on designing and implementing a DMF platform on a PCB. This involves:

1. Hardware Design and Integration: Designing a PCB layout to support electrode patterns necessary for droplet manipulation. The design must enable precise control of droplet movement across the platform, incorporating key components like driving electronics, electrode arrays, and control circuits.

2. Electronics and Control Systems: Developing and implementing a control system to power the electrodes, allowing selective activation for droplet control. You will have the opportunity to work with microcontrollers and control interfaces for automated droplet manipulation.

3. Testing and Optimization: Conducting experiments to validate the functionality of the DMF platform, evaluating parameters such as droplet speed, control accuracy, and system robustness. This includes troubleshooting and optimizing the system for reliable performance.

Requirements:

• Background in Hardware Design: Familiarity with PCB design is essential. Experience with software tools like Altium Designer, Eagle, or KiCad is highly preferred.
• Knowledge of Electronics Fundamentals: Understanding of microcontrollers, signal processing, and basic circuit design will be beneficial for the control system aspects of the project.
• Interest in Microfluidics or Biomedical Engineering: While prior experience in microfluidics is not required, an enthusiasm for learning about microfluidic systems and applications will be invaluable.

What You Will Gain:

• Practical experience in PCB design and hardware integration for microfluidic applications.
• Insight into the principles and applications of digital microfluidics.
• The opportunity to contribute to the development of cutting-edge technology with potential applications in diagnostics, biology, and chemistry.

If you are a proactive learner with a passion for electronics and an interest in microfluidics, we invite you to apply for this exciting project. This is a unique chance to apply your technical skills to an emerging area with broad interdisciplinary applications.

AI models keep growing faster than the devices that have to run them. The techniques that work at data-centre scale are exactly the ones unavailable on a battery-powered sensor node, a wearable, or a microcontroller, and a surprising number of published efficiency methods quietly assume otherwise. That mismatch leaves a great deal of untapped territory.

This open topic is aimed at students who want to go beyond a predefined project and explore their own research direction in efficient machine learning.

We are particularly interested in novel and creative approaches, including (but not limited to):

• Compression and quantization: new formats, new sensitivity criteria, or compression designed around what the target hardware can express
• On-device learning: adaptation, continual and federated learning under memory budgets measured in kilobytes
• Efficient architectures for constrained devices: compact transformers, state-space models, event-driven computation
• Hardware-software co-design: mapping, custom instructions, in-memory computing, or accelerator-aware algorithm design
• Benchmarking, measurement and tooling that makes efficiency claims verifiable rather than merely reported
• Completely new ideas that challenge existing assumptions

The goal is to develop a promising direction into a meaningful project, with the potential to grow into a thesis or a publication depending on the interest and the goal. We will help you refine and scope the idea.

Voraussetzungen

A model frozen at deployment slowly stops working. Sensors drift, users differ from the training population, devices are worn or mounted differently. Adapting on the device itself is the natural answer, but training is far more expensive than inference, and these devices have kilobytes of memory rathen than gigabytes.

The usual assumption is that fewer trainable parameters means less training memory. That comes from large language models, where optimizer state dominates, and it is wrong for embedded convolutional networks, where memory is dominated by the activations that automatic differentiation retains between the forward and backward pass. This difference opens more questions than it closes for edge training.

Depending on your interest and background, possible directions include (but are not limited to):

Memory-Efficient Adaptation

- Adapter and update designs whose backward pass provably never touches a full-width activation tensor

- Joint scheduling of freezing, recomputation and activation compression under a fixed byte budget, and what binds once saved activations are gone

Training Under Low-Precision Arithmetic

- Quantized backward passes, low-precision optimizer states and gradient quantization for devices without floating-point units

- Adapters that merge exactly on an integer backend, or fold into per-channel quantization scales rather than into the weight tensor

Learning Without Labels, and Continually

- Test-time adaptation, self-supervision on sensor streams and cross-sensor pseudo-labelling

- Stability on non-stationary streams, forgetting under kilobyte-scale replay buffers, and federated personalization across devices

Deployment, Measurement and Hardware Support

- Port memory-efficient training rules into an embedded runtime and measure real peak SRAM, latency and energy

- What hardware support would actually help on-device training, at the instruction, memory-hierarchy or dataflow level

Your Own Direction

- If you already have a question about training or adaptation on constrained devices that you want to pursue, bring it. A good idea from you is a better starting point than one from us

The work can lean toward algorithms, toward embedded systems and measurement, or toward co-design.

[1] H. Cai, C. Gan, L. Zhu, S. Han, “TinyTL: Reduce Memory, Not Parameters for Efficient On-Device Learning,” NeurIPS 2020. arXiv:2007.11622.

[2] J. Lin et al., “On-Device Training Under 256KB Memory,” NeurIPS 2022. arXiv:2206.15472.

[3] S. Patil et al., “POET: Training Neural Networks on Tiny Devices with Integrated Rematerialization and Paging,” ICML 2022. arXiv:2207.07697.

[4] E. J. Hu et al., “LoRA: Low-Rank Adaptation of Large Language Models,” ICLR 2022. arXiv:2106.09685.

[5] Y.-D. Kwon et al., “TinyTrain: Resource-Aware Task-Adaptive Sparse Training of DNNs at the Data-Scarce Edge,” ICML 2024. arXiv:2307.09988.

[6] D. Nadalini, M. Rusci, L. Benini, F. Conti, “Reduced precision floating-point optimization for DNN on-device learning on microcontrollers,” Future Generation Computer Systems 149 (2023) 212–226.

Voraussetzungen

Modern neural networks are far larger than the devices meant to run them, and quantization is what closes most of that gap. It is also the technique with the widest open research surface: what works for a convolutional network does not transfer to a transformer-based model, post-training methods break down in the low-bit regime, and the hardware the models must run on is changing underneath the algorithms.

Most of the field also optimizes proxies to understand quantization sensitivity under different bit precisions. Also most papers report model size, BitOps, or compression ratio, while what decides whether a model runs on a microcontroller is memory traffic, peak SRAM, and what the instruction set can actually express.

Recent research on precision allocation measures a layer's sensitivity based on various statistics such as the information flowing through the whole network rather than by a local property, Hessian information, Fisher information etc, which can be a working starting point, and a source of open questions.

Rather than prescribing a fixed path, we will scope a concrete contribution together, depending on your interests and background. Possible directions include (but are not limited to):

Quantization Algorithms

- Post-training quantization: calibration, outlier and rotation-based preprocessing, and the low-bit regime where post-training methods start to fail

- Quantization-aware training: gradient estimators, learned scales and clipping, and stability below four bits

Precision Allocation and Numeric Formats

- To answer which layers deserve which precision: sensitivity criteria compared under one common allocator, and allocation as an integer program under an explicit budget

- Block floating-point and microscaling formats (MXFP4, MXFP6, MXINT8, NVFP4), non-uniform grids, and quantization for analog compute-in-memory where a device noise floor caps how many bits are useful

Compression Beyond Quantization, and Beyond CNNs

- Structured and semi-structured pruning, low-rank factorization and distillation and whether stacked techniques compose or cancel

- Compact transformers and state-space models, where activations, KV cache and recurrent state, not weights, dominate the budget

Hardware-Aware Objectives and Co-Design

- Replace BitOps and size proxies with cost models fitted to real microcontroller and RISC-V measurements, and put them inside the search loop

- Co-optimize per-layer precision with dataflow and tiling, and explore custom RISC-V instructions for sub-byte kernels using the chair's compiler and simulator tooling

Your Own Direction

- If you already have a question in quantization or compression that you want to pursue, bring it. A good idea from you is a better starting point than one from us.

The work can lean toward algorithms and theory, toward systems and deployment, or toward hardware-software co-design. We aim to produce publishable research results, making this a good opportunity for students interested in academia or advanced R&D.

References

[1] Nagel, Markus et al. “A White Paper on Neural Network Quantization.” ArXiv abs/2106.08295 (2021)

[2] Gholami, Amir et al. “A Survey of Quantization Methods for Efficient Neural Network Inference.” ArXiv abs/2103.13630 (2021)

[3] Akbulut, Mehmet Emre et al. “InfoQ: Mixed-Precision Quantization via Global Information Flow.” AAAI 2026. ArXiv abs/2508.04753 (2026)

[4] Dong, Zhen et al. “HAWQ-V2: Hessian Aware trace-Weighted Quantization of Neural Networks.”, NeurIPS 2020. ArXiv abs/1911.03852 (2020)

[5] Frantar, Elias et al. “GPTQ: Accurate Post-Training Quantization for Generative Pre-trained Transformers.”, ICLR 2023. ArXiv abs/2210.17323 (2023)

[6] P. van Kempen et al., “MLonMCU: TinyML Benchmarking with Fast Retargeting,” CODAI 2023. arXiv:2306.08951.

Voraussetzungen

Modern deep neural networks (DNNs) require substantial memory for intermediate activations, which can become a major bottleneck when deploying models on memory-constrained edge devices and accelerators. Spatial or input tiling addresses this problem by dividing intermediate tensors into smaller regions that can be processed independently. Approaches such as Fused Depthwise Tiling (FDT) exploit this principle across multiple operators, reducing peak activation memory by avoiding the materialization of complete intermediate feature maps [1].

However, tiled execution introduces additional challenges. Convolutional operators require neighboring input elements around each output tile, resulting in overlapping halo regions. When tiling is propagated through longer operator chains, these regions can grow and introduce increasingly redundant computation and data movement. Choosing suitable tile sizes and deciding how far tiling should be propagated therefore creates a trade-off between peak memory consumption, redundant computation, and execution performance.

The IREE compiler provides an MLIR-based compilation infrastructure for deploying machine-learning workloads across heterogeneous hardware platforms [2]. Its existing support for tiling, fusion, and workload distribution provides a suitable foundation for implementing memory-oriented DNN tiling strategies. Furthermore, work such as TinyIREE demonstrates the relevance of IREE for resource-constrained DNN inference [3].

This project investigates the integration and evaluation of such tiling techniques within IREE. Possible directions include:

• Design and implementation of an MLIR/IREE compiler pass for spatial or input tiling of DNN operators

• Propagation of tiles across multiple operators to avoid materializing complete intermediate tensors

• Integration with existing IREE tiling, fusion, and lowering infrastructure

• Evaluation of peak memory usage, execution latency, and computational overhead

• Automated exploration of tile sizes and tiling/fusion strategies

• Investigation of strategies for mitigating increasing halo overhead across longer tiled operator chains

[1] Stahl, R., Mueller-Gritschneder, D., & Schlichtmann, U. (2023). Fused depthwise tiling for memory optimization in tinyml deep neural network inference. arXiv preprint arXiv:2303.17878.

[2] https://github.com/iree-org/iree

[3] Hsin-I Cindy Liu, Marius Brehler, Mahesh Ravishankar, Nicolas Vasilache, Ben Vanik, and Stella Laurenzo. 2022. TinyIREE: An ML Execution Environment for Embedded Systems From Compilation to Deployment. IEEE Micro 42, 5 (Sept.-Oct. 2022), 9–16. https://doi.org/10.1109/MM.2022.3178068 

Voraussetzungen

Modern DNN accelerators increasingly employ heterogeneous multi-core and chiplet-based architectures to meet the growing computational demands of deep learning. Besides distributing computation across multiple accelerator cores, these systems increasingly integrate multiple off-chip memory resources, such as HBM stacks, distributed DRAM controllers, or chiplet-local memories. Efficient placement of tensors across these memories is crucial for reducing communication overhead, balancing memory bandwidth, and improving overall inference performance. However, the Stream design space exploration framework currently assumes a single off-chip memory, limiting its applicability to emerging distributed memory architectures [1].

Memory placement has been extensively studied in related domains, including NUMA systems [2], heterogeneous memory architectures, and multi-chiplet GPUs [3], where locality-aware placement, bandwidth balancing, and memory migration are key optimization techniques. More recently, locality-aware tensor placement across multiple HBM stacks has been shown to significantly reduce remote memory accesses and improve execution efficiency in chiplet-based systems [4]. Similar challenges arise for DNN accelerators, where the placement of weights and activations directly impacts communication, memory utilization, and execution efficiency. Nevertheless, distributed off-chip memory placement for heterogeneous DNN accelerator architectures remains largely unexplored.

This project investigates off-chip memory placement strategies for heterogeneous DNN accelerators by extending the Stream DSE framework. Possible directions include:

• Extending Stream to support multiple distributed off-chip memories
• Investigation of memory placement strategies for weights and activations
• Static and heuristic-based tensor placement algorithms
• Analysis of communication, bandwidth, latency, and energy trade-offs
• Evaluation on heterogeneous and chiplet-based accelerator architectures

References

[1] A. Symons, L. Mei, S. Colleman, P. Houshmand, S. Karl and M. Verhelst, "Stream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators," IEEE Transactions on Computers, vol. 74, no. 1, pp. 237–249, Jan. 2025.

[2] D. Gureya et al., "Bandwidth-Aware Page Placement in NUMA," 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), New Orleans, LA, USA, 2020, pp. 546-556, doi: 10.1109/IPDPS47924.2020.00063.

[3] Park, J., Jang, S., Kwon, O., Lee, Y., & Hong, S. (2025, October). Leveraging Chiplet-Locality for Efficient Memory Mapping in Multi-Chip Module GPUs. In Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture (pp. 1040-1057).

[4] Chung, E., Ju, J. H., & Kim, H. (2026). Making Locality-aware GEMM Compatible with Page-Granularity Placement on Chiplet GPUs. arXiv preprint arXiv:2606.11718.

Voraussetzungen

Hardware-Aware Acceleration of Large-Scale MIQP Optimization for Future Chiplet Systems

Future chiplet-based systems require complex decisions about how workloads should be partitioned, mapped, and scheduled across multiple interconnected processing elements. At the chair, an optimization framework has been developed that formulates these decisions as a mixed-integer quadratic programming problem. The framework jointly considers objectives such as execution time, communication cost, energy consumption, and resource utilization.

Although modern GPUs provide substantial acceleration for many scientific and machine-learning workloads, their advantages are much more limited for mixed-integer optimization. State-of-the-art MIQP solvers are commonly based on branch-and-bound and related search procedures. These algorithms involve irregular control flow, dynamically evolving search trees, frequent synchronization, and memory-access patterns that are difficult to parallelize efficiently on conventional GPUs. As a result, solver performance often remains strongly dependent on CPU execution.

However, defining the “best CPU” for this workload is not straightforward. Solver performance may depend on many architectural properties, including single-thread performance, core count, cache capacity, memory bandwidth, memory latency, NUMA behavior, vector capabilities, and communication overhead between cores. At the same time, emerging computing platforms and specialized architectures may offer new opportunities for accelerating irregular optimization workloads.

In this research project, you will investigate how different hardware architectures affect the performance of large-scale MIQP-based scheduling and partitioning problems. The project will begin with a systematic benchmarking study across available computing platforms. Based on the observed bottlenecks, you will then develop and evaluate strategies that exploit the strengths of each architecture more effectively.

Possible research directions include:

• benchmarking CPUs with different core, cache, memory, and NUMA characteristics,
• analyzing solver behavior at the root relaxation and throughout the branch-and-bound tree,
• identifying which solver phases are limited by computation, memory access, synchronization, or search efficiency,
• evaluating many-core CPUs and heterogeneous computing platforms,
• investigating emerging architectures designed for irregular, graph-oriented, or combinatorial workloads,
• optimizing thread placement, memory allocation, solver parameters, and parallel search strategies,
• designing workload-aware strategies for selecting hardware and solver configurations,
• and exploring hybrid approaches in which selected solver components are offloaded to accelerators.

The project should go beyond reporting total runtime. Detailed profiling should be used to understand how hardware characteristics influence node processing speed, relaxation solving, cut generation, heuristic execution, memory consumption, synchronization overhead, and the evolution of primal and dual bounds.

A central goal is to determine whether different stages of the optimization process benefit from different hardware characteristics. This may enable adaptive strategies that select solver configurations dynamically, distribute work across heterogeneous resources, or assign specific subproblems to the architecture best suited to them.

Voraussetzungen

This project investigates automatic synthesis of multi-function RISC-V hardware accelerators for edge computing cores. It will extend uhLS [1], a compact, open-source High-level Hardware Synthesis (HLS) framework that lowers C code through intermediate representations into drivers, RTL, and ASIC-oriented flows, enabling the synthesis of several functions into a single shared accelerator block.

The goal is to synthesize multiple kernels, for example, DSP operations and AI inference primitives, into a single tightly coupled accelerator attached to a RISC-V processor pipeline. The main focus is on resource reuse across functions, especially shared multipliers, adders, memories, register files, and control logic, instead of generating one accelerator per function.

The thesis will extend the uhLS scheduling, binding, and backend flow to support multiple top-level functions, a shared datapath, and a dispatch/control mechanism. The generated accelerator should expose custom RISC-V instructions through a tightly coupled interface, with CV-X-IF/CORE-V-XIF [4] and SCAIE-V [5] as possible candidates, as they support external coprocessor-style instruction extensions without modifying the CPU RTL.

A second focus is synchronization. The project should compare statically timed accelerators, where latency is known to the compiler or to the issue logic, with explicit synchronization, such as ready/valid handshakes, status polling, or special synchronization instructions. The toolchain should reuse CoreDSL2 [2] for ISA/custom-instruction descriptions, and Seal5 [3] to generate LLVM [6]/compiler support for those custom instructions.

Related Work:

[1] µhLS / uhLS: Micro High-Level Synthesis Tool. https://github.com/JoGei/uhls

[2] CoreDSL2: ISA Description Language. Domain-specific language for modeling instruction-set architectures and custom ISA extensions; relevant as the architectural description layer for custom instructions.https://minres.github.io/CoreDSL/

[3] P. Van Kempen, M. Salmen, D. Mueller-Gritschneder, and U. Schlichtmann, "Seal5: Semi-Automated LLVM Support for RISC-V ISA Extensions Including Autovectorization," 2024 27th Euromicro Conference on Digital System Design (DSD), Paris, France, 2024, pp. 335-342, doi: 10.1109/DSD64264.2024.00052.

[4] OpenHW CORE-V-XIF / CV-X-IF Specification. Standardized RISC-V extension interface. https://docs.openhwgroup.org/projects/openhw-group-core-v-xif/en/latest/intro.html

[5] SCAIE-V. Open-source scalable interface for RISC-V ISA extensions.https://github.com/esa-tu-darmstadt/SCAIE-V-2.0

[6] Lattner, Chris, and Vikram Adve. "LLVM: A compilation framework for lifelong program analysis & transformation." International symposium on code generation and optimization, 2004. CGO 2004.. IEEE, 2004.

Voraussetzungen

Project Overview

Digital Microfluidics (DMF) is a cutting-edge technology that enables the precise manipulation of minute fluid volumes (droplets) via electrical actuation. We currently have a functional web-based design tool that allows researchers to create custom PCB-based and glass-based DMF chips. This platform streamlines the transition from concept to manufacturable hardware by providing features like custom electrode placement, automated routing, and experiment definition.

We are looking for motivated students to join our follow-up project. The goal is to extend the platform's functional modules and refine the core routing algorithms to handle increasingly complex chip architectures.

Tasks

As a student on this project, you will focus on two primary areas:

1. Platform Extension & Feature Enhancement

• Integrated Path Planning: Develop an automated droplet path planning feature where users can select start and end points, and the system generates the optimal movement sequence.
• Functional Module Libraries: Create templates and interfaces for specialized biological and chemical detection modules to improve design efficiency for specific experimental scenarios.
• Advanced UI/UX: Enhance the interactive editor, building upon existing features like "undo/redo," "copy/paste," and the "parallel electrode" batch processing system.

2. Routing Algorithm Refinement

• Algorithm Optimization: Work with our existing WebAssembly (WASM) and Web Worker-based routing engine to improve performance and success rates for high-density designs.
• Geometric Refinement: Modify the grid-based routing and collision detection logic to support finer electrode spacings and complex trace widths.
• Via Management: Refine the dynamic via cost mechanisms to optimize vertical interconnections between PCB layers.

Technical Environment

You will work with a modern, high-performance tech stack:

• Frontend: Vue 3, Element Plus, and SVG for vector graphics rendering.
• Core Logic: C++ (compiled to WebAssembly) for heavy computational tasks.
• Communication: Web Serial API for real-time hardware interfacing.
• Hardware Integration: Exporting KiCad-compatible files for physical PCB manufacturing.

Requirements

• Strong interest in Electronic Design Automation (EDA) or Microfluidics.
• Proficiency in JavaScript/TypeScript (preferably Vue 3) or C++.
• Basic understanding of geometric algorithms or PCB design is a plus.

Robust and Explainable Cas13d Guide RNA Design

RNA-targeting CRISPR systems such as Cas13d have emerged as powerful tools for programmable transcriptome engineering. While STOA frameworks improve practical guide RNA design using sequence-only deep learning models and interpretable interfaces, important challenges remain unresolved. Current systems primarily optimize predicted efficacy, while real-world applications require balancing multiple objectives including specificity, robustness across transcripts, structural accessibility, and uncertainty estimation.

This project aims to develop a next-generation design automation framework that performs multi-objective and uncertainty-aware guide RNA optimization for Cas13d systems. The student will investigate how deep learning architectures can jointly model guide efficacy, off-target risk, transcript accessibility, and confidence estimation using only computationally obtainable information.

The project may include:

• designing improved hybrid architectures (Transformer/CNN/attention-based models),
• integrating RNA secondary structure predictions or accessibility priors,
• developing uncertainty-aware ranking methods,
• implementing multi-objective scoring and candidate ranking,
• creating explainability methods for sequence-level interpretation,
• evaluating generalization across transcripts or datasets,
• and optionally extending the interactive natural-language explanation interface.

The final outcome should be a deployable prototype that produces ranked and interpretable guide RNA candidates from raw transcript sequences while improving robustness and transparency in practical CRISPR RNA-targeting workflows.

Possible Research Questions

• Can uncertainty estimation improve trustworthiness in guide RNA ranking?
• How can off-target risk and efficacy be jointly optimized?
• Which sequence motifs or contextual interactions most strongly determine Cas13d activity?
• Can RNA structure-aware representations improve prediction using only computational inputs?
• How transferable are learned guide design principles across datasets or organisms?

Voraussetzungen

As data communication demands in many-core systems grow dramatically,networks-on-chip (NoCs) have emerged as an efficient framework for on-chip communication. Electrical Networks-on-Chip (ENoCs) and Wavelength-Routed Optical Networks-on-Chip (WRONoCs) are both considered promising solutions. WRONoCs provide high bandwidth and low latency, while the data transmission of ENoCs is more energy-efficient. To combine their advantages, hybrid Electrical-Optical Networks-on-Chip have been proposed by integrating both transmission paradigms, allowing data to be transmitted through either electrical or optical paths. However, whether such combined architectures can fully realize their potential largely depends on how task mapping is performed. Over time, however, aging-induced issues can make the system increasingly asymmetric, which in turn necessitates adjustments to the task-mapping strategy.

Voraussetzungen

The intersection of artificial intelligence and hardware/system design is rapidly evolving. Many traditional problems in areas such as chip design, optimization, and system architecture are being revisited with modern machine learning techniques—yet there is still vast untapped potential for new ideas.

This open topic is aimed at students who want to go beyond predefined projects and instead explore their own research direction. We are particularly interested in novel and creative approaches, including (but not limited to):

• Applying machine learning to classical hardware or EDA problems
• Reinforcement learning or optimization for system design and scheduling
• AI-driven design space exploration or co-design approaches
• Using modern paradigms such as foundation models or autonomous research/optimization agents
• Completely new ideas that challenge existing workflows or assumptions

The goal is to identify promising research directions and develop them into meaningful projects, with the potential to grow into a thesis or even a research publication.

You will work closely with supervision to refine your idea, scope the problem, and develop a concrete research plan—but the starting point should come from you.

Voraussetzungen

Modern chip design involves increasingly complex optimization problems, in which millions of interdependent design decisions must be made under strict physical and performance constraints. One central problem in this area is macro placement: arranging large components, such as SRAM blocks and intellectual property modules, on a chip while jointly optimizing routing congestion, timing, power delivery, wirelength, and area utilization.

Macro placement is inherently challenging. It combines a highly discrete and constrained search space with multiple competing objectives and strong global dependencies between placement decisions. Classical placement methods have been refined over decades and remain highly effective, but recent advances in machine learning and generative modeling offer promising opportunities to complement or improve existing approaches.

In this research internship, you will develop and evaluate novel methods for macro placement and related combinatorial optimization problems. The goal is to investigate algorithms that can scale to large, highly constrained systems while producing high-quality solutions within realistic runtime limits.

Possible research directions include:

• reinforcement learning and graph neural network approaches,
• generative methods such as diffusion models for producing or refining placements,
• hybrid methods combining machine learning with classical heuristics or mathematical optimization,
• learned search, ranking, or proposal mechanisms,
• scalable approximation and local-search techniques,
• and improvements to established placement algorithms using modern machine-learning and optimization tooling.

A particular emphasis may be placed on exploring how generative models can learn distributions over high-quality placements, incorporate physical and design-rule constraints, and guide downstream search or refinement procedures. Rather than replacing established optimization methods entirely, such models may serve as initialization mechanisms, proposal generators, surrogate models, or components within hybrid optimization pipelines.

The developed approaches will be evaluated on representative macro-placement benchmarks using relevant physical-design metrics, including wirelength, congestion, timing-related proxies, constraint satisfaction, solution quality, scalability, and runtime.

Voraussetzungen

Recent advances in AI/ML models (e.g., large language models) demand unprecedented compute and memory resources, making efficient system design a central challenge. New approaches, such as energy-aware co-optimization of hardware architectures and workload execution, enable significant improvements in energy-delay efficiency and scalability .

This thesis builds on such optimization-driven frameworks and opens up a range of possible research directions. Rather than prescribing a fixed path, the goal is to let you explore and define your own contribution within this space, depending on your interests.

Possible directions include (but are not limited to):

• Optimization & Algorithms
  • Improve scalability and efficiency of optimization solvers (e.g., MIQP-based approaches)
  • Develop approximation, heuristic, or hybrid optimization techniques
  • Explore alternative formulations for large-scale design space exploration
• AI for Systems / Learning-Based Methods
  • Investigate reinforcement learning or learning-based approaches for scheduling, mapping, or architecture design
  • Compare learned vs. analytical optimization strategies
• Scalable Systems & Workloads
  • Extend analyses to extremely large workloads (e.g., LLM-scale systems)
  • Study trade-offs between performance, energy, and hardware constraints
• Hardware & Architecture Exploration
  • Analyze emerging architectures such as multi-chiplet systems
  • Explore memory hierarchies, interconnects, and power management strategies
• Tooling & Visualization
  • Develop intuitive interfaces or visual analytics tools for design space exploration
  • Make complex optimization results interpretable and interactive

The work can be adapted toward a more theoretical, systems-oriented, or practical/software-driven thesis. We aim to produce publishable research results, making this an excellent opportunity for students interested in academia or advanced R&D.

Voraussetzungen

Emerging computing architectures increasingly rely on chiplet-based systems and distributed execution to efficiently run complex workloads such as AI inference. In such systems, computations and intermediate results are exchanged between multiple processing units. Ensuring the integrity and correctness of these computations becomes an important challenge, particularly in the presence of hardware faults, communication errors, or malicious manipulation.

Techniques for detecting computational errors have long been studied, for example, through Algorithm-based Fault Tolerance (ABFT) methods for linear algebra operations [1]. More recently, similar concepts have been explored for machine learning workloads and NN inference, where protecting intermediate results and detecting corrupted computations is becoming increasingly important [2], [3], [4], [5]. At the same time, emerging architectures such as chiplet-based systems introduce new challenges for ensuring reliable execution across distributed compute units.

This student project investigates mechanisms for verifying the correctness of distributed AI computations in heterogeneous and chiplet-based architectures. Possible directions include:

• Techniques for integrity verification of distributed AI inference

• Detection of faults or corrupted intermediate results

• Lightweight verification mechanisms based on algorithmic or system-level approaches

• Analysis of trade-offs between reliability, performance, and overhead

References

[1] Kuang-Hua Huang and J. A. Abraham, "Algorithm-Based Fault Tolerance for Matrix Operations," in IEEE Transactions on Computers, vol. C-33, no. 6, pp. 518-528, June 1984, doi: 10.1109/TC.1984.1676475.

[2] S. K. S. Hari, M. B. Sullivan, T. Tsai and S. W. Keckler, "Making Convolutions Resilient Via Algorithm-Based Error Detection Techniques," in IEEE Transactions on Dependable and Secure Computing, vol. 19, no. 4, pp. 2546-2558, 1 July-Aug. 2022, doi: 10.1109/TDSC.2021.3063083.

[3] J. Hoefer, M. Stammler, F. Kreß, T. Hotfilter, T. Harbaum and J. Becker, "BayWatch: Leveraging Bayesian Neural Networks for Hardware Fault Tolerance and Monitoring," 2024 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Didcot, United Kingdom, 2024, pp. 1-6, doi: 10.1109/DFT63277.2024.10753546.

[4] Z. Chen, G. Li and K. Pattabiraman, "A Low-cost Fault Corrector for Deep Neural Networks through Range Restriction," in IEEE Design & Test, doi: 10.1109/MDAT.2025.3618758.

[5] J. Kappes, J. Geier, P. van Kempen, D. Mueller-Gritschneder and U. Schlichtmann, "Automated Graph-level Passes for TinyML Fault Tolerance," 2025 International Joint Conference on Neural Networks (IJCNN), Rome, Italy, 2025, pp. 1-9, doi: 10.1109/IJCNN64981.2025.11227379.

Voraussetzungen

Are you interested in hands-on experience in the emerging field of microfluidics? We are seeking a motivated student to join an innovative project focused on developing a PCB (Printed Circuit Board)-based digital microfluidics (DMF) platform. This project offers an excellent opportunity to apply your knowledge of hardware and PCB design while diving into the fascinating world of microfluidics.

About Digital Microfluidics (DMF):

Digital microfluidics (DMF) is a technology that allows precise manipulation of tiny droplets on a microscale using electrical fields. Unlike continuous-flow microfluidics, which relies on channels and pumps, DMF provides flexibility by enabling individual droplets to be moved, merged, split, or mixed on an open surface. This droplet-based control offers a powerful approach for various applications, from biomedical assays to chemical synthesis, with the benefit of reconfigurability and automation.

Project Scope:

In this project, you will focus on designing and implementing a DMF platform on a PCB. This involves:

1. Hardware Design and Integration: Designing a PCB layout to support electrode patterns necessary for droplet manipulation. The design must enable precise control of droplet movement across the platform, incorporating key components like driving electronics, electrode arrays, and control circuits.

2. Electronics and Control Systems: Developing and implementing a control system to power the electrodes, allowing selective activation for droplet control. You will have the opportunity to work with microcontrollers and control interfaces for automated droplet manipulation.

3. Testing and Optimization: Conducting experiments to validate the functionality of the DMF platform, evaluating parameters such as droplet speed, control accuracy, and system robustness. This includes troubleshooting and optimizing the system for reliable performance.

Requirements:

• Background in Hardware Design: Familiarity with PCB design is essential. Experience with software tools like Altium Designer, Eagle, or KiCad is highly preferred.
• Knowledge of Electronics Fundamentals: Understanding of microcontrollers, signal processing, and basic circuit design will be beneficial for the control system aspects of the project.
• Interest in Microfluidics or Biomedical Engineering: While prior experience in microfluidics is not required, an enthusiasm for learning about microfluidic systems and applications will be invaluable.

What You Will Gain:

• Practical experience in PCB design and hardware integration for microfluidic applications.
• Insight into the principles and applications of digital microfluidics.
• The opportunity to contribute to the development of cutting-edge technology with potential applications in diagnostics, biology, and chemistry.

If you are a proactive learner with a passion for electronics and an interest in microfluidics, we invite you to apply for this exciting project. This is a unique chance to apply your technical skills to an emerging area with broad interdisciplinary applications.

AI models keep growing faster than the devices that have to run them. The techniques that work at data-centre scale are exactly the ones unavailable on a battery-powered sensor node, a wearable, or a microcontroller, and a surprising number of published efficiency methods quietly assume otherwise. That mismatch leaves a great deal of untapped territory.

This open topic is aimed at students who want to go beyond a predefined project and explore their own research direction in efficient machine learning.

We are particularly interested in novel and creative approaches, including (but not limited to):

• Compression and quantization: new formats, new sensitivity criteria, or compression designed around what the target hardware can express
• On-device learning: adaptation, continual and federated learning under memory budgets measured in kilobytes
• Efficient architectures for constrained devices: compact transformers, state-space models, event-driven computation
• Hardware-software co-design: mapping, custom instructions, in-memory computing, or accelerator-aware algorithm design
• Benchmarking, measurement and tooling that makes efficiency claims verifiable rather than merely reported
• Completely new ideas that challenge existing assumptions

The goal is to develop a promising direction into a meaningful project, with the potential to grow into a thesis or a publication depending on the interest and the goal. We will help you refine and scope the idea.

Voraussetzungen

A model frozen at deployment slowly stops working. Sensors drift, users differ from the training population, devices are worn or mounted differently. Adapting on the device itself is the natural answer, but training is far more expensive than inference, and these devices have kilobytes of memory rathen than gigabytes.

The usual assumption is that fewer trainable parameters means less training memory. That comes from large language models, where optimizer state dominates, and it is wrong for embedded convolutional networks, where memory is dominated by the activations that automatic differentiation retains between the forward and backward pass. This difference opens more questions than it closes for edge training.

Depending on your interest and background, possible directions include (but are not limited to):

Memory-Efficient Adaptation

- Adapter and update designs whose backward pass provably never touches a full-width activation tensor

- Joint scheduling of freezing, recomputation and activation compression under a fixed byte budget, and what binds once saved activations are gone

Training Under Low-Precision Arithmetic

- Quantized backward passes, low-precision optimizer states and gradient quantization for devices without floating-point units

- Adapters that merge exactly on an integer backend, or fold into per-channel quantization scales rather than into the weight tensor

Learning Without Labels, and Continually

- Test-time adaptation, self-supervision on sensor streams and cross-sensor pseudo-labelling

- Stability on non-stationary streams, forgetting under kilobyte-scale replay buffers, and federated personalization across devices

Deployment, Measurement and Hardware Support

- Port memory-efficient training rules into an embedded runtime and measure real peak SRAM, latency and energy

- What hardware support would actually help on-device training, at the instruction, memory-hierarchy or dataflow level

Your Own Direction

- If you already have a question about training or adaptation on constrained devices that you want to pursue, bring it. A good idea from you is a better starting point than one from us

The work can lean toward algorithms, toward embedded systems and measurement, or toward co-design.

[1] H. Cai, C. Gan, L. Zhu, S. Han, “TinyTL: Reduce Memory, Not Parameters for Efficient On-Device Learning,” NeurIPS 2020. arXiv:2007.11622.

[2] J. Lin et al., “On-Device Training Under 256KB Memory,” NeurIPS 2022. arXiv:2206.15472.

[3] S. Patil et al., “POET: Training Neural Networks on Tiny Devices with Integrated Rematerialization and Paging,” ICML 2022. arXiv:2207.07697.

[4] E. J. Hu et al., “LoRA: Low-Rank Adaptation of Large Language Models,” ICLR 2022. arXiv:2106.09685.

[5] Y.-D. Kwon et al., “TinyTrain: Resource-Aware Task-Adaptive Sparse Training of DNNs at the Data-Scarce Edge,” ICML 2024. arXiv:2307.09988.

[6] D. Nadalini, M. Rusci, L. Benini, F. Conti, “Reduced precision floating-point optimization for DNN on-device learning on microcontrollers,” Future Generation Computer Systems 149 (2023) 212–226.

Voraussetzungen

Modern neural networks are far larger than the devices meant to run them, and quantization is what closes most of that gap. It is also the technique with the widest open research surface: what works for a convolutional network does not transfer to a transformer-based model, post-training methods break down in the low-bit regime, and the hardware the models must run on is changing underneath the algorithms.

Most of the field also optimizes proxies to understand quantization sensitivity under different bit precisions. Also most papers report model size, BitOps, or compression ratio, while what decides whether a model runs on a microcontroller is memory traffic, peak SRAM, and what the instruction set can actually express.

Recent research on precision allocation measures a layer's sensitivity based on various statistics such as the information flowing through the whole network rather than by a local property, Hessian information, Fisher information etc, which can be a working starting point, and a source of open questions.

Rather than prescribing a fixed path, we will scope a concrete contribution together, depending on your interests and background. Possible directions include (but are not limited to):

Quantization Algorithms

- Post-training quantization: calibration, outlier and rotation-based preprocessing, and the low-bit regime where post-training methods start to fail

- Quantization-aware training: gradient estimators, learned scales and clipping, and stability below four bits

Precision Allocation and Numeric Formats

- To answer which layers deserve which precision: sensitivity criteria compared under one common allocator, and allocation as an integer program under an explicit budget

- Block floating-point and microscaling formats (MXFP4, MXFP6, MXINT8, NVFP4), non-uniform grids, and quantization for analog compute-in-memory where a device noise floor caps how many bits are useful

Compression Beyond Quantization, and Beyond CNNs

- Structured and semi-structured pruning, low-rank factorization and distillation and whether stacked techniques compose or cancel

- Compact transformers and state-space models, where activations, KV cache and recurrent state, not weights, dominate the budget

Hardware-Aware Objectives and Co-Design

- Replace BitOps and size proxies with cost models fitted to real microcontroller and RISC-V measurements, and put them inside the search loop

- Co-optimize per-layer precision with dataflow and tiling, and explore custom RISC-V instructions for sub-byte kernels using the chair's compiler and simulator tooling

Your Own Direction

- If you already have a question in quantization or compression that you want to pursue, bring it. A good idea from you is a better starting point than one from us.

The work can lean toward algorithms and theory, toward systems and deployment, or toward hardware-software co-design. We aim to produce publishable research results, making this a good opportunity for students interested in academia or advanced R&D.

References

[1] Nagel, Markus et al. “A White Paper on Neural Network Quantization.” ArXiv abs/2106.08295 (2021)

[2] Gholami, Amir et al. “A Survey of Quantization Methods for Efficient Neural Network Inference.” ArXiv abs/2103.13630 (2021)

[3] Akbulut, Mehmet Emre et al. “InfoQ: Mixed-Precision Quantization via Global Information Flow.” AAAI 2026. ArXiv abs/2508.04753 (2026)

[4] Dong, Zhen et al. “HAWQ-V2: Hessian Aware trace-Weighted Quantization of Neural Networks.”, NeurIPS 2020. ArXiv abs/1911.03852 (2020)

[5] Frantar, Elias et al. “GPTQ: Accurate Post-Training Quantization for Generative Pre-trained Transformers.”, ICLR 2023. ArXiv abs/2210.17323 (2023)

[6] P. van Kempen et al., “MLonMCU: TinyML Benchmarking with Fast Retargeting,” CODAI 2023. arXiv:2306.08951.

Voraussetzungen

Hardware-Aware Acceleration of Large-Scale MIQP Optimization for Future Chiplet Systems

Future chiplet-based systems require complex decisions about how workloads should be partitioned, mapped, and scheduled across multiple interconnected processing elements. At the chair, an optimization framework has been developed that formulates these decisions as a mixed-integer quadratic programming problem. The framework jointly considers objectives such as execution time, communication cost, energy consumption, and resource utilization.

Although modern GPUs provide substantial acceleration for many scientific and machine-learning workloads, their advantages are much more limited for mixed-integer optimization. State-of-the-art MIQP solvers are commonly based on branch-and-bound and related search procedures. These algorithms involve irregular control flow, dynamically evolving search trees, frequent synchronization, and memory-access patterns that are difficult to parallelize efficiently on conventional GPUs. As a result, solver performance often remains strongly dependent on CPU execution.

However, defining the “best CPU” for this workload is not straightforward. Solver performance may depend on many architectural properties, including single-thread performance, core count, cache capacity, memory bandwidth, memory latency, NUMA behavior, vector capabilities, and communication overhead between cores. At the same time, emerging computing platforms and specialized architectures may offer new opportunities for accelerating irregular optimization workloads.

In this research project, you will investigate how different hardware architectures affect the performance of large-scale MIQP-based scheduling and partitioning problems. The project will begin with a systematic benchmarking study across available computing platforms. Based on the observed bottlenecks, you will then develop and evaluate strategies that exploit the strengths of each architecture more effectively.

Possible research directions include:

• benchmarking CPUs with different core, cache, memory, and NUMA characteristics,
• analyzing solver behavior at the root relaxation and throughout the branch-and-bound tree,
• identifying which solver phases are limited by computation, memory access, synchronization, or search efficiency,
• evaluating many-core CPUs and heterogeneous computing platforms,
• investigating emerging architectures designed for irregular, graph-oriented, or combinatorial workloads,
• optimizing thread placement, memory allocation, solver parameters, and parallel search strategies,
• designing workload-aware strategies for selecting hardware and solver configurations,
• and exploring hybrid approaches in which selected solver components are offloaded to accelerators.

The project should go beyond reporting total runtime. Detailed profiling should be used to understand how hardware characteristics influence node processing speed, relaxation solving, cut generation, heuristic execution, memory consumption, synchronization overhead, and the evolution of primal and dual bounds.

A central goal is to determine whether different stages of the optimization process benefit from different hardware characteristics. This may enable adaptive strategies that select solver configurations dynamically, distribute work across heterogeneous resources, or assign specific subproblems to the architecture best suited to them.

Voraussetzungen

Project Overview

Digital Microfluidics (DMF) is a cutting-edge technology that enables the precise manipulation of minute fluid volumes (droplets) via electrical actuation. We currently have a functional web-based design tool that allows researchers to create custom PCB-based and glass-based DMF chips. This platform streamlines the transition from concept to manufacturable hardware by providing features like custom electrode placement, automated routing, and experiment definition.

We are looking for motivated students to join our follow-up project. The goal is to extend the platform's functional modules and refine the core routing algorithms to handle increasingly complex chip architectures.

Tasks

As a student on this project, you will focus on two primary areas:

1. Platform Extension & Feature Enhancement

• Integrated Path Planning: Develop an automated droplet path planning feature where users can select start and end points, and the system generates the optimal movement sequence.
• Functional Module Libraries: Create templates and interfaces for specialized biological and chemical detection modules to improve design efficiency for specific experimental scenarios.
• Advanced UI/UX: Enhance the interactive editor, building upon existing features like "undo/redo," "copy/paste," and the "parallel electrode" batch processing system.

2. Routing Algorithm Refinement

• Algorithm Optimization: Work with our existing WebAssembly (WASM) and Web Worker-based routing engine to improve performance and success rates for high-density designs.
• Geometric Refinement: Modify the grid-based routing and collision detection logic to support finer electrode spacings and complex trace widths.
• Via Management: Refine the dynamic via cost mechanisms to optimize vertical interconnections between PCB layers.

Technical Environment

You will work with a modern, high-performance tech stack:

• Frontend: Vue 3, Element Plus, and SVG for vector graphics rendering.
• Core Logic: C++ (compiled to WebAssembly) for heavy computational tasks.
• Communication: Web Serial API for real-time hardware interfacing.
• Hardware Integration: Exporting KiCad-compatible files for physical PCB manufacturing.

Requirements

• Strong interest in Electronic Design Automation (EDA) or Microfluidics.
• Proficiency in JavaScript/TypeScript (preferably Vue 3) or C++.
• Basic understanding of geometric algorithms or PCB design is a plus.

Robust and Explainable Cas13d Guide RNA Design

RNA-targeting CRISPR systems such as Cas13d have emerged as powerful tools for programmable transcriptome engineering. While STOA frameworks improve practical guide RNA design using sequence-only deep learning models and interpretable interfaces, important challenges remain unresolved. Current systems primarily optimize predicted efficacy, while real-world applications require balancing multiple objectives including specificity, robustness across transcripts, structural accessibility, and uncertainty estimation.

This project aims to develop a next-generation design automation framework that performs multi-objective and uncertainty-aware guide RNA optimization for Cas13d systems. The student will investigate how deep learning architectures can jointly model guide efficacy, off-target risk, transcript accessibility, and confidence estimation using only computationally obtainable information.

The project may include:

• designing improved hybrid architectures (Transformer/CNN/attention-based models),
• integrating RNA secondary structure predictions or accessibility priors,
• developing uncertainty-aware ranking methods,
• implementing multi-objective scoring and candidate ranking,
• creating explainability methods for sequence-level interpretation,
• evaluating generalization across transcripts or datasets,
• and optionally extending the interactive natural-language explanation interface.

The final outcome should be a deployable prototype that produces ranked and interpretable guide RNA candidates from raw transcript sequences while improving robustness and transparency in practical CRISPR RNA-targeting workflows.

Possible Research Questions

• Can uncertainty estimation improve trustworthiness in guide RNA ranking?
• How can off-target risk and efficacy be jointly optimized?
• Which sequence motifs or contextual interactions most strongly determine Cas13d activity?
• Can RNA structure-aware representations improve prediction using only computational inputs?
• How transferable are learned guide design principles across datasets or organisms?

Voraussetzungen

The intersection of artificial intelligence and hardware/system design is rapidly evolving. Many traditional problems in areas such as chip design, optimization, and system architecture are being revisited with modern machine learning techniques—yet there is still vast untapped potential for new ideas.

This open topic is aimed at students who want to go beyond predefined projects and instead explore their own research direction. We are particularly interested in novel and creative approaches, including (but not limited to):

• Applying machine learning to classical hardware or EDA problems
• Reinforcement learning or optimization for system design and scheduling
• AI-driven design space exploration or co-design approaches
• Using modern paradigms such as foundation models or autonomous research/optimization agents
• Completely new ideas that challenge existing workflows or assumptions

The goal is to identify promising research directions and develop them into meaningful projects, with the potential to grow into a thesis or even a research publication.

You will work closely with supervision to refine your idea, scope the problem, and develop a concrete research plan—but the starting point should come from you.

Voraussetzungen

Modern chip design involves increasingly complex optimization problems, in which millions of interdependent design decisions must be made under strict physical and performance constraints. One central problem in this area is macro placement: arranging large components, such as SRAM blocks and intellectual property modules, on a chip while jointly optimizing routing congestion, timing, power delivery, wirelength, and area utilization.

Macro placement is inherently challenging. It combines a highly discrete and constrained search space with multiple competing objectives and strong global dependencies between placement decisions. Classical placement methods have been refined over decades and remain highly effective, but recent advances in machine learning and generative modeling offer promising opportunities to complement or improve existing approaches.

In this research internship, you will develop and evaluate novel methods for macro placement and related combinatorial optimization problems. The goal is to investigate algorithms that can scale to large, highly constrained systems while producing high-quality solutions within realistic runtime limits.

Possible research directions include:

• reinforcement learning and graph neural network approaches,
• generative methods such as diffusion models for producing or refining placements,
• hybrid methods combining machine learning with classical heuristics or mathematical optimization,
• learned search, ranking, or proposal mechanisms,
• scalable approximation and local-search techniques,
• and improvements to established placement algorithms using modern machine-learning and optimization tooling.

A particular emphasis may be placed on exploring how generative models can learn distributions over high-quality placements, incorporate physical and design-rule constraints, and guide downstream search or refinement procedures. Rather than replacing established optimization methods entirely, such models may serve as initialization mechanisms, proposal generators, surrogate models, or components within hybrid optimization pipelines.

The developed approaches will be evaluated on representative macro-placement benchmarks using relevant physical-design metrics, including wirelength, congestion, timing-related proxies, constraint satisfaction, solution quality, scalability, and runtime.

Voraussetzungen

Recent advances in AI/ML models (e.g., large language models) demand unprecedented compute and memory resources, making efficient system design a central challenge. New approaches, such as energy-aware co-optimization of hardware architectures and workload execution, enable significant improvements in energy-delay efficiency and scalability .

This thesis builds on such optimization-driven frameworks and opens up a range of possible research directions. Rather than prescribing a fixed path, the goal is to let you explore and define your own contribution within this space, depending on your interests.

Possible directions include (but are not limited to):

• Optimization & Algorithms
  • Improve scalability and efficiency of optimization solvers (e.g., MIQP-based approaches)
  • Develop approximation, heuristic, or hybrid optimization techniques
  • Explore alternative formulations for large-scale design space exploration
• AI for Systems / Learning-Based Methods
  • Investigate reinforcement learning or learning-based approaches for scheduling, mapping, or architecture design
  • Compare learned vs. analytical optimization strategies
• Scalable Systems & Workloads
  • Extend analyses to extremely large workloads (e.g., LLM-scale systems)
  • Study trade-offs between performance, energy, and hardware constraints
• Hardware & Architecture Exploration
  • Analyze emerging architectures such as multi-chiplet systems
  • Explore memory hierarchies, interconnects, and power management strategies
• Tooling & Visualization
  • Develop intuitive interfaces or visual analytics tools for design space exploration
  • Make complex optimization results interpretable and interactive

The work can be adapted toward a more theoretical, systems-oriented, or practical/software-driven thesis. We aim to produce publishable research results, making this an excellent opportunity for students interested in academia or advanced R&D.

Voraussetzungen

Are you interested in hands-on experience in the emerging field of microfluidics? We are seeking a motivated student to join an innovative project focused on developing a PCB (Printed Circuit Board)-based digital microfluidics (DMF) platform. This project offers an excellent opportunity to apply your knowledge of hardware and PCB design while diving into the fascinating world of microfluidics.

About Digital Microfluidics (DMF):

Digital microfluidics (DMF) is a technology that allows precise manipulation of tiny droplets on a microscale using electrical fields. Unlike continuous-flow microfluidics, which relies on channels and pumps, DMF provides flexibility by enabling individual droplets to be moved, merged, split, or mixed on an open surface. This droplet-based control offers a powerful approach for various applications, from biomedical assays to chemical synthesis, with the benefit of reconfigurability and automation.

Project Scope:

In this project, you will focus on designing and implementing a DMF platform on a PCB. This involves:

1. Hardware Design and Integration: Designing a PCB layout to support electrode patterns necessary for droplet manipulation. The design must enable precise control of droplet movement across the platform, incorporating key components like driving electronics, electrode arrays, and control circuits.

2. Electronics and Control Systems: Developing and implementing a control system to power the electrodes, allowing selective activation for droplet control. You will have the opportunity to work with microcontrollers and control interfaces for automated droplet manipulation.

3. Testing and Optimization: Conducting experiments to validate the functionality of the DMF platform, evaluating parameters such as droplet speed, control accuracy, and system robustness. This includes troubleshooting and optimizing the system for reliable performance.

Requirements:

• Background in Hardware Design: Familiarity with PCB design is essential. Experience with software tools like Altium Designer, Eagle, or KiCad is highly preferred.
• Knowledge of Electronics Fundamentals: Understanding of microcontrollers, signal processing, and basic circuit design will be beneficial for the control system aspects of the project.
• Interest in Microfluidics or Biomedical Engineering: While prior experience in microfluidics is not required, an enthusiasm for learning about microfluidic systems and applications will be invaluable.

What You Will Gain:

• Practical experience in PCB design and hardware integration for microfluidic applications.
• Insight into the principles and applications of digital microfluidics.
• The opportunity to contribute to the development of cutting-edge technology with potential applications in diagnostics, biology, and chemistry.

If you are a proactive learner with a passion for electronics and an interest in microfluidics, we invite you to apply for this exciting project. This is a unique chance to apply your technical skills to an emerging area with broad interdisciplinary applications.

AI models keep growing faster than the devices that have to run them. The techniques that work at data-centre scale are exactly the ones unavailable on a battery-powered sensor node, a wearable, or a microcontroller, and a surprising number of published efficiency methods quietly assume otherwise. That mismatch leaves a great deal of untapped territory.

This open topic is aimed at students who want to go beyond a predefined project and explore their own research direction in efficient machine learning.

We are particularly interested in novel and creative approaches, including (but not limited to):

• Compression and quantization: new formats, new sensitivity criteria, or compression designed around what the target hardware can express
• On-device learning: adaptation, continual and federated learning under memory budgets measured in kilobytes
• Efficient architectures for constrained devices: compact transformers, state-space models, event-driven computation
• Hardware-software co-design: mapping, custom instructions, in-memory computing, or accelerator-aware algorithm design
• Benchmarking, measurement and tooling that makes efficiency claims verifiable rather than merely reported
• Completely new ideas that challenge existing assumptions

The goal is to develop a promising direction into a meaningful project, with the potential to grow into a thesis or a publication depending on the interest and the goal. We will help you refine and scope the idea.

Voraussetzungen

A model frozen at deployment slowly stops working. Sensors drift, users differ from the training population, devices are worn or mounted differently. Adapting on the device itself is the natural answer, but training is far more expensive than inference, and these devices have kilobytes of memory rathen than gigabytes.

The usual assumption is that fewer trainable parameters means less training memory. That comes from large language models, where optimizer state dominates, and it is wrong for embedded convolutional networks, where memory is dominated by the activations that automatic differentiation retains between the forward and backward pass. This difference opens more questions than it closes for edge training.

Depending on your interest and background, possible directions include (but are not limited to):

Memory-Efficient Adaptation

- Adapter and update designs whose backward pass provably never touches a full-width activation tensor

- Joint scheduling of freezing, recomputation and activation compression under a fixed byte budget, and what binds once saved activations are gone

Training Under Low-Precision Arithmetic

- Quantized backward passes, low-precision optimizer states and gradient quantization for devices without floating-point units

- Adapters that merge exactly on an integer backend, or fold into per-channel quantization scales rather than into the weight tensor

Learning Without Labels, and Continually

- Test-time adaptation, self-supervision on sensor streams and cross-sensor pseudo-labelling

- Stability on non-stationary streams, forgetting under kilobyte-scale replay buffers, and federated personalization across devices

Deployment, Measurement and Hardware Support

- Port memory-efficient training rules into an embedded runtime and measure real peak SRAM, latency and energy

- What hardware support would actually help on-device training, at the instruction, memory-hierarchy or dataflow level

Your Own Direction

- If you already have a question about training or adaptation on constrained devices that you want to pursue, bring it. A good idea from you is a better starting point than one from us

The work can lean toward algorithms, toward embedded systems and measurement, or toward co-design.

[1] H. Cai, C. Gan, L. Zhu, S. Han, “TinyTL: Reduce Memory, Not Parameters for Efficient On-Device Learning,” NeurIPS 2020. arXiv:2007.11622.

[2] J. Lin et al., “On-Device Training Under 256KB Memory,” NeurIPS 2022. arXiv:2206.15472.

[3] S. Patil et al., “POET: Training Neural Networks on Tiny Devices with Integrated Rematerialization and Paging,” ICML 2022. arXiv:2207.07697.

[4] E. J. Hu et al., “LoRA: Low-Rank Adaptation of Large Language Models,” ICLR 2022. arXiv:2106.09685.

[5] Y.-D. Kwon et al., “TinyTrain: Resource-Aware Task-Adaptive Sparse Training of DNNs at the Data-Scarce Edge,” ICML 2024. arXiv:2307.09988.

[6] D. Nadalini, M. Rusci, L. Benini, F. Conti, “Reduced precision floating-point optimization for DNN on-device learning on microcontrollers,” Future Generation Computer Systems 149 (2023) 212–226.

Voraussetzungen

Modern neural networks are far larger than the devices meant to run them, and quantization is what closes most of that gap. It is also the technique with the widest open research surface: what works for a convolutional network does not transfer to a transformer-based model, post-training methods break down in the low-bit regime, and the hardware the models must run on is changing underneath the algorithms.

Most of the field also optimizes proxies to understand quantization sensitivity under different bit precisions. Also most papers report model size, BitOps, or compression ratio, while what decides whether a model runs on a microcontroller is memory traffic, peak SRAM, and what the instruction set can actually express.

Recent research on precision allocation measures a layer's sensitivity based on various statistics such as the information flowing through the whole network rather than by a local property, Hessian information, Fisher information etc, which can be a working starting point, and a source of open questions.

Rather than prescribing a fixed path, we will scope a concrete contribution together, depending on your interests and background. Possible directions include (but are not limited to):

Quantization Algorithms

- Post-training quantization: calibration, outlier and rotation-based preprocessing, and the low-bit regime where post-training methods start to fail

- Quantization-aware training: gradient estimators, learned scales and clipping, and stability below four bits

Precision Allocation and Numeric Formats

- To answer which layers deserve which precision: sensitivity criteria compared under one common allocator, and allocation as an integer program under an explicit budget

- Block floating-point and microscaling formats (MXFP4, MXFP6, MXINT8, NVFP4), non-uniform grids, and quantization for analog compute-in-memory where a device noise floor caps how many bits are useful

Compression Beyond Quantization, and Beyond CNNs

- Structured and semi-structured pruning, low-rank factorization and distillation and whether stacked techniques compose or cancel

- Compact transformers and state-space models, where activations, KV cache and recurrent state, not weights, dominate the budget

Hardware-Aware Objectives and Co-Design

- Replace BitOps and size proxies with cost models fitted to real microcontroller and RISC-V measurements, and put them inside the search loop

- Co-optimize per-layer precision with dataflow and tiling, and explore custom RISC-V instructions for sub-byte kernels using the chair's compiler and simulator tooling

Your Own Direction

- If you already have a question in quantization or compression that you want to pursue, bring it. A good idea from you is a better starting point than one from us.

The work can lean toward algorithms and theory, toward systems and deployment, or toward hardware-software co-design. We aim to produce publishable research results, making this a good opportunity for students interested in academia or advanced R&D.

References

[1] Nagel, Markus et al. “A White Paper on Neural Network Quantization.” ArXiv abs/2106.08295 (2021)

[2] Gholami, Amir et al. “A Survey of Quantization Methods for Efficient Neural Network Inference.” ArXiv abs/2103.13630 (2021)

[3] Akbulut, Mehmet Emre et al. “InfoQ: Mixed-Precision Quantization via Global Information Flow.” AAAI 2026. ArXiv abs/2508.04753 (2026)

[4] Dong, Zhen et al. “HAWQ-V2: Hessian Aware trace-Weighted Quantization of Neural Networks.”, NeurIPS 2020. ArXiv abs/1911.03852 (2020)

[5] Frantar, Elias et al. “GPTQ: Accurate Post-Training Quantization for Generative Pre-trained Transformers.”, ICLR 2023. ArXiv abs/2210.17323 (2023)

[6] P. van Kempen et al., “MLonMCU: TinyML Benchmarking with Fast Retargeting,” CODAI 2023. arXiv:2306.08951.

Voraussetzungen

Modern deep neural networks (DNNs) require substantial memory for intermediate activations, which can become a major bottleneck when deploying models on memory-constrained edge devices and accelerators. Spatial or input tiling addresses this problem by dividing intermediate tensors into smaller regions that can be processed independently. Approaches such as Fused Depthwise Tiling (FDT) exploit this principle across multiple operators, reducing peak activation memory by avoiding the materialization of complete intermediate feature maps [1].

However, tiled execution introduces additional challenges. Convolutional operators require neighboring input elements around each output tile, resulting in overlapping halo regions. When tiling is propagated through longer operator chains, these regions can grow and introduce increasingly redundant computation and data movement. Choosing suitable tile sizes and deciding how far tiling should be propagated therefore creates a trade-off between peak memory consumption, redundant computation, and execution performance.

The IREE compiler provides an MLIR-based compilation infrastructure for deploying machine-learning workloads across heterogeneous hardware platforms [2]. Its existing support for tiling, fusion, and workload distribution provides a suitable foundation for implementing memory-oriented DNN tiling strategies. Furthermore, work such as TinyIREE demonstrates the relevance of IREE for resource-constrained DNN inference [3].

This project investigates the integration and evaluation of such tiling techniques within IREE. Possible directions include:

• Design and implementation of an MLIR/IREE compiler pass for spatial or input tiling of DNN operators

• Propagation of tiles across multiple operators to avoid materializing complete intermediate tensors

• Integration with existing IREE tiling, fusion, and lowering infrastructure

• Evaluation of peak memory usage, execution latency, and computational overhead

• Automated exploration of tile sizes and tiling/fusion strategies

• Investigation of strategies for mitigating increasing halo overhead across longer tiled operator chains

[1] Stahl, R., Mueller-Gritschneder, D., & Schlichtmann, U. (2023). Fused depthwise tiling for memory optimization in tinyml deep neural network inference. arXiv preprint arXiv:2303.17878.

[2] https://github.com/iree-org/iree

[3] Hsin-I Cindy Liu, Marius Brehler, Mahesh Ravishankar, Nicolas Vasilache, Ben Vanik, and Stella Laurenzo. 2022. TinyIREE: An ML Execution Environment for Embedded Systems From Compilation to Deployment. IEEE Micro 42, 5 (Sept.-Oct. 2022), 9–16. https://doi.org/10.1109/MM.2022.3178068 

Voraussetzungen

Modern DNN accelerators increasingly employ heterogeneous multi-core and chiplet-based architectures to meet the growing computational demands of deep learning. Besides distributing computation across multiple accelerator cores, these systems increasingly integrate multiple off-chip memory resources, such as HBM stacks, distributed DRAM controllers, or chiplet-local memories. Efficient placement of tensors across these memories is crucial for reducing communication overhead, balancing memory bandwidth, and improving overall inference performance. However, the Stream design space exploration framework currently assumes a single off-chip memory, limiting its applicability to emerging distributed memory architectures [1].

Memory placement has been extensively studied in related domains, including NUMA systems [2], heterogeneous memory architectures, and multi-chiplet GPUs [3], where locality-aware placement, bandwidth balancing, and memory migration are key optimization techniques. More recently, locality-aware tensor placement across multiple HBM stacks has been shown to significantly reduce remote memory accesses and improve execution efficiency in chiplet-based systems [4]. Similar challenges arise for DNN accelerators, where the placement of weights and activations directly impacts communication, memory utilization, and execution efficiency. Nevertheless, distributed off-chip memory placement for heterogeneous DNN accelerator architectures remains largely unexplored.

This project investigates off-chip memory placement strategies for heterogeneous DNN accelerators by extending the Stream DSE framework. Possible directions include:

• Extending Stream to support multiple distributed off-chip memories
• Investigation of memory placement strategies for weights and activations
• Static and heuristic-based tensor placement algorithms
• Analysis of communication, bandwidth, latency, and energy trade-offs
• Evaluation on heterogeneous and chiplet-based accelerator architectures

References

[1] A. Symons, L. Mei, S. Colleman, P. Houshmand, S. Karl and M. Verhelst, "Stream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators," IEEE Transactions on Computers, vol. 74, no. 1, pp. 237–249, Jan. 2025.

[2] D. Gureya et al., "Bandwidth-Aware Page Placement in NUMA," 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), New Orleans, LA, USA, 2020, pp. 546-556, doi: 10.1109/IPDPS47924.2020.00063.

[3] Park, J., Jang, S., Kwon, O., Lee, Y., & Hong, S. (2025, October). Leveraging Chiplet-Locality for Efficient Memory Mapping in Multi-Chip Module GPUs. In Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture (pp. 1040-1057).

[4] Chung, E., Ju, J. H., & Kim, H. (2026). Making Locality-aware GEMM Compatible with Page-Granularity Placement on Chiplet GPUs. arXiv preprint arXiv:2606.11718.

Voraussetzungen

Hardware-Aware Acceleration of Large-Scale MIQP Optimization for Future Chiplet Systems

Future chiplet-based systems require complex decisions about how workloads should be partitioned, mapped, and scheduled across multiple interconnected processing elements. At the chair, an optimization framework has been developed that formulates these decisions as a mixed-integer quadratic programming problem. The framework jointly considers objectives such as execution time, communication cost, energy consumption, and resource utilization.

Although modern GPUs provide substantial acceleration for many scientific and machine-learning workloads, their advantages are much more limited for mixed-integer optimization. State-of-the-art MIQP solvers are commonly based on branch-and-bound and related search procedures. These algorithms involve irregular control flow, dynamically evolving search trees, frequent synchronization, and memory-access patterns that are difficult to parallelize efficiently on conventional GPUs. As a result, solver performance often remains strongly dependent on CPU execution.

However, defining the “best CPU” for this workload is not straightforward. Solver performance may depend on many architectural properties, including single-thread performance, core count, cache capacity, memory bandwidth, memory latency, NUMA behavior, vector capabilities, and communication overhead between cores. At the same time, emerging computing platforms and specialized architectures may offer new opportunities for accelerating irregular optimization workloads.

In this research project, you will investigate how different hardware architectures affect the performance of large-scale MIQP-based scheduling and partitioning problems. The project will begin with a systematic benchmarking study across available computing platforms. Based on the observed bottlenecks, you will then develop and evaluate strategies that exploit the strengths of each architecture more effectively.

Possible research directions include:

• benchmarking CPUs with different core, cache, memory, and NUMA characteristics,
• analyzing solver behavior at the root relaxation and throughout the branch-and-bound tree,
• identifying which solver phases are limited by computation, memory access, synchronization, or search efficiency,
• evaluating many-core CPUs and heterogeneous computing platforms,
• investigating emerging architectures designed for irregular, graph-oriented, or combinatorial workloads,
• optimizing thread placement, memory allocation, solver parameters, and parallel search strategies,
• designing workload-aware strategies for selecting hardware and solver configurations,
• and exploring hybrid approaches in which selected solver components are offloaded to accelerators.

The project should go beyond reporting total runtime. Detailed profiling should be used to understand how hardware characteristics influence node processing speed, relaxation solving, cut generation, heuristic execution, memory consumption, synchronization overhead, and the evolution of primal and dual bounds.

A central goal is to determine whether different stages of the optimization process benefit from different hardware characteristics. This may enable adaptive strategies that select solver configurations dynamically, distribute work across heterogeneous resources, or assign specific subproblems to the architecture best suited to them.

Voraussetzungen

This project investigates automatic synthesis of multi-function RISC-V hardware accelerators for edge computing cores. It will extend uhLS [1], a compact, open-source High-level Hardware Synthesis (HLS) framework that lowers C code through intermediate representations into drivers, RTL, and ASIC-oriented flows, enabling the synthesis of several functions into a single shared accelerator block.

The goal is to synthesize multiple kernels, for example, DSP operations and AI inference primitives, into a single tightly coupled accelerator attached to a RISC-V processor pipeline. The main focus is on resource reuse across functions, especially shared multipliers, adders, memories, register files, and control logic, instead of generating one accelerator per function.

The thesis will extend the uhLS scheduling, binding, and backend flow to support multiple top-level functions, a shared datapath, and a dispatch/control mechanism. The generated accelerator should expose custom RISC-V instructions through a tightly coupled interface, with CV-X-IF/CORE-V-XIF [4] and SCAIE-V [5] as possible candidates, as they support external coprocessor-style instruction extensions without modifying the CPU RTL.

A second focus is synchronization. The project should compare statically timed accelerators, where latency is known to the compiler or to the issue logic, with explicit synchronization, such as ready/valid handshakes, status polling, or special synchronization instructions. The toolchain should reuse CoreDSL2 [2] for ISA/custom-instruction descriptions, and Seal5 [3] to generate LLVM [6]/compiler support for those custom instructions.

Related Work:

[1] µhLS / uhLS: Micro High-Level Synthesis Tool. https://github.com/JoGei/uhls

[2] CoreDSL2: ISA Description Language. Domain-specific language for modeling instruction-set architectures and custom ISA extensions; relevant as the architectural description layer for custom instructions.https://minres.github.io/CoreDSL/

[3] P. Van Kempen, M. Salmen, D. Mueller-Gritschneder, and U. Schlichtmann, "Seal5: Semi-Automated LLVM Support for RISC-V ISA Extensions Including Autovectorization," 2024 27th Euromicro Conference on Digital System Design (DSD), Paris, France, 2024, pp. 335-342, doi: 10.1109/DSD64264.2024.00052.

[4] OpenHW CORE-V-XIF / CV-X-IF Specification. Standardized RISC-V extension interface. https://docs.openhwgroup.org/projects/openhw-group-core-v-xif/en/latest/intro.html

[5] SCAIE-V. Open-source scalable interface for RISC-V ISA extensions.https://github.com/esa-tu-darmstadt/SCAIE-V-2.0

[6] Lattner, Chris, and Vikram Adve. "LLVM: A compilation framework for lifelong program analysis & transformation." International symposium on code generation and optimization, 2004. CGO 2004.. IEEE, 2004.

Voraussetzungen

Robust and Explainable Cas13d Guide RNA Design

RNA-targeting CRISPR systems such as Cas13d have emerged as powerful tools for programmable transcriptome engineering. While STOA frameworks improve practical guide RNA design using sequence-only deep learning models and interpretable interfaces, important challenges remain unresolved. Current systems primarily optimize predicted efficacy, while real-world applications require balancing multiple objectives including specificity, robustness across transcripts, structural accessibility, and uncertainty estimation.

This project aims to develop a next-generation design automation framework that performs multi-objective and uncertainty-aware guide RNA optimization for Cas13d systems. The student will investigate how deep learning architectures can jointly model guide efficacy, off-target risk, transcript accessibility, and confidence estimation using only computationally obtainable information.

The project may include:

• designing improved hybrid architectures (Transformer/CNN/attention-based models),
• integrating RNA secondary structure predictions or accessibility priors,
• developing uncertainty-aware ranking methods,
• implementing multi-objective scoring and candidate ranking,
• creating explainability methods for sequence-level interpretation,
• evaluating generalization across transcripts or datasets,
• and optionally extending the interactive natural-language explanation interface.

The final outcome should be a deployable prototype that produces ranked and interpretable guide RNA candidates from raw transcript sequences while improving robustness and transparency in practical CRISPR RNA-targeting workflows.

Possible Research Questions

• Can uncertainty estimation improve trustworthiness in guide RNA ranking?
• How can off-target risk and efficacy be jointly optimized?
• Which sequence motifs or contextual interactions most strongly determine Cas13d activity?
• Can RNA structure-aware representations improve prediction using only computational inputs?
• How transferable are learned guide design principles across datasets or organisms?

Voraussetzungen

As data communication demands in many-core systems grow dramatically,networks-on-chip (NoCs) have emerged as an efficient framework for on-chip communication. Electrical Networks-on-Chip (ENoCs) and Wavelength-Routed Optical Networks-on-Chip (WRONoCs) are both considered promising solutions. WRONoCs provide high bandwidth and low latency, while the data transmission of ENoCs is more energy-efficient. To combine their advantages, hybrid Electrical-Optical Networks-on-Chip have been proposed by integrating both transmission paradigms, allowing data to be transmitted through either electrical or optical paths. However, whether such combined architectures can fully realize their potential largely depends on how task mapping is performed. Over time, however, aging-induced issues can make the system increasingly asymmetric, which in turn necessitates adjustments to the task-mapping strategy.

Voraussetzungen

The intersection of artificial intelligence and hardware/system design is rapidly evolving. Many traditional problems in areas such as chip design, optimization, and system architecture are being revisited with modern machine learning techniques—yet there is still vast untapped potential for new ideas.

This open topic is aimed at students who want to go beyond predefined projects and instead explore their own research direction. We are particularly interested in novel and creative approaches, including (but not limited to):

• Applying machine learning to classical hardware or EDA problems
• Reinforcement learning or optimization for system design and scheduling
• AI-driven design space exploration or co-design approaches
• Using modern paradigms such as foundation models or autonomous research/optimization agents
• Completely new ideas that challenge existing workflows or assumptions

The goal is to identify promising research directions and develop them into meaningful projects, with the potential to grow into a thesis or even a research publication.

You will work closely with supervision to refine your idea, scope the problem, and develop a concrete research plan—but the starting point should come from you.

Voraussetzungen

Modern chip design involves increasingly complex optimization problems, in which millions of interdependent design decisions must be made under strict physical and performance constraints. One central problem in this area is macro placement: arranging large components, such as SRAM blocks and intellectual property modules, on a chip while jointly optimizing routing congestion, timing, power delivery, wirelength, and area utilization.

Macro placement is inherently challenging. It combines a highly discrete and constrained search space with multiple competing objectives and strong global dependencies between placement decisions. Classical placement methods have been refined over decades and remain highly effective, but recent advances in machine learning and generative modeling offer promising opportunities to complement or improve existing approaches.

In this research internship, you will develop and evaluate novel methods for macro placement and related combinatorial optimization problems. The goal is to investigate algorithms that can scale to large, highly constrained systems while producing high-quality solutions within realistic runtime limits.

Possible research directions include:

• reinforcement learning and graph neural network approaches,
• generative methods such as diffusion models for producing or refining placements,
• hybrid methods combining machine learning with classical heuristics or mathematical optimization,
• learned search, ranking, or proposal mechanisms,
• scalable approximation and local-search techniques,
• and improvements to established placement algorithms using modern machine-learning and optimization tooling.

A particular emphasis may be placed on exploring how generative models can learn distributions over high-quality placements, incorporate physical and design-rule constraints, and guide downstream search or refinement procedures. Rather than replacing established optimization methods entirely, such models may serve as initialization mechanisms, proposal generators, surrogate models, or components within hybrid optimization pipelines.

The developed approaches will be evaluated on representative macro-placement benchmarks using relevant physical-design metrics, including wirelength, congestion, timing-related proxies, constraint satisfaction, solution quality, scalability, and runtime.

Voraussetzungen

Recent advances in AI/ML models (e.g., large language models) demand unprecedented compute and memory resources, making efficient system design a central challenge. New approaches, such as energy-aware co-optimization of hardware architectures and workload execution, enable significant improvements in energy-delay efficiency and scalability .

This thesis builds on such optimization-driven frameworks and opens up a range of possible research directions. Rather than prescribing a fixed path, the goal is to let you explore and define your own contribution within this space, depending on your interests.

Possible directions include (but are not limited to):

• Optimization & Algorithms
  • Improve scalability and efficiency of optimization solvers (e.g., MIQP-based approaches)
  • Develop approximation, heuristic, or hybrid optimization techniques
  • Explore alternative formulations for large-scale design space exploration
• AI for Systems / Learning-Based Methods
  • Investigate reinforcement learning or learning-based approaches for scheduling, mapping, or architecture design
  • Compare learned vs. analytical optimization strategies
• Scalable Systems & Workloads
  • Extend analyses to extremely large workloads (e.g., LLM-scale systems)
  • Study trade-offs between performance, energy, and hardware constraints
• Hardware & Architecture Exploration
  • Analyze emerging architectures such as multi-chiplet systems
  • Explore memory hierarchies, interconnects, and power management strategies
• Tooling & Visualization
  • Develop intuitive interfaces or visual analytics tools for design space exploration
  • Make complex optimization results interpretable and interactive

The work can be adapted toward a more theoretical, systems-oriented, or practical/software-driven thesis. We aim to produce publishable research results, making this an excellent opportunity for students interested in academia or advanced R&D.

Voraussetzungen

Power dissipation of integrated circuits (IC) is crucial, as it directly influences the battery life of edge devices, but also the cooling requirements for servers. To get to power-aware IC designs, precise power modeling is crucial in the design flow. Usually, this is done by a mapping of input features, like input signal activities or the number of gates in the design, to dynamic, static, or total power. Here, recently, machine learning (ML)-based models are in focus. 

The drawback of ML-based models is their limited transferability from circuit designs used in training to unseen circuits. Foundation models, like large language models, have shown great potential in other domains through their generalizability. Hence, they could also support here in the transferability problem of power modeling. Foundation models specifically designed for ICs, like the NetTAG [1], have been proposed. But, it is still open if these complex frameworks provide a significant benefit to power modeling.

The goal of this project is:

- Getting familiar with the NetTAG framework and its adapted version at the chair

- Design a downstream task for power estimation

- Evaluation of the transferability of NetTAG+downstream task

[1] Fang, Wenji, et al. "Nettag: A multimodal rtl-and-layout-aligned netlist foundation model via text-attributed graph." 2025 62nd ACM/IEEE Design Automation Conference (DAC). IEEE, 2025.

Voraussetzungen

Emerging computing architectures increasingly rely on chiplet-based systems and distributed execution to efficiently run complex workloads such as AI inference. In such systems, computations and intermediate results are exchanged between multiple processing units. Ensuring the integrity and correctness of these computations becomes an important challenge, particularly in the presence of hardware faults, communication errors, or malicious manipulation.

Techniques for detecting computational errors have long been studied, for example, through Algorithm-based Fault Tolerance (ABFT) methods for linear algebra operations [1]. More recently, similar concepts have been explored for machine learning workloads and NN inference, where protecting intermediate results and detecting corrupted computations is becoming increasingly important [2], [3], [4], [5]. At the same time, emerging architectures such as chiplet-based systems introduce new challenges for ensuring reliable execution across distributed compute units.

This student project investigates mechanisms for verifying the correctness of distributed AI computations in heterogeneous and chiplet-based architectures. Possible directions include:

• Techniques for integrity verification of distributed AI inference

• Detection of faults or corrupted intermediate results

• Lightweight verification mechanisms based on algorithmic or system-level approaches

• Analysis of trade-offs between reliability, performance, and overhead

References

[1] Kuang-Hua Huang and J. A. Abraham, "Algorithm-Based Fault Tolerance for Matrix Operations," in IEEE Transactions on Computers, vol. C-33, no. 6, pp. 518-528, June 1984, doi: 10.1109/TC.1984.1676475.

[2] S. K. S. Hari, M. B. Sullivan, T. Tsai and S. W. Keckler, "Making Convolutions Resilient Via Algorithm-Based Error Detection Techniques," in IEEE Transactions on Dependable and Secure Computing, vol. 19, no. 4, pp. 2546-2558, 1 July-Aug. 2022, doi: 10.1109/TDSC.2021.3063083.

[3] J. Hoefer, M. Stammler, F. Kreß, T. Hotfilter, T. Harbaum and J. Becker, "BayWatch: Leveraging Bayesian Neural Networks for Hardware Fault Tolerance and Monitoring," 2024 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Didcot, United Kingdom, 2024, pp. 1-6, doi: 10.1109/DFT63277.2024.10753546.

[4] Z. Chen, G. Li and K. Pattabiraman, "A Low-cost Fault Corrector for Deep Neural Networks through Range Restriction," in IEEE Design & Test, doi: 10.1109/MDAT.2025.3618758.

[5] J. Kappes, J. Geier, P. van Kempen, D. Mueller-Gritschneder and U. Schlichtmann, "Automated Graph-level Passes for TinyML Fault Tolerance," 2025 International Joint Conference on Neural Networks (IJCNN), Rome, Italy, 2025, pp. 1-9, doi: 10.1109/IJCNN64981.2025.11227379.

Voraussetzungen

Hardware-Aware Acceleration of Large-Scale MIQP Optimization for Future Chiplet Systems

Future chiplet-based systems require complex decisions about how workloads should be partitioned, mapped, and scheduled across multiple interconnected processing elements. At the chair, an optimization framework has been developed that formulates these decisions as a mixed-integer quadratic programming problem. The framework jointly considers objectives such as execution time, communication cost, energy consumption, and resource utilization.

Although modern GPUs provide substantial acceleration for many scientific and machine-learning workloads, their advantages are much more limited for mixed-integer optimization. State-of-the-art MIQP solvers are commonly based on branch-and-bound and related search procedures. These algorithms involve irregular control flow, dynamically evolving search trees, frequent synchronization, and memory-access patterns that are difficult to parallelize efficiently on conventional GPUs. As a result, solver performance often remains strongly dependent on CPU execution.

However, defining the “best CPU” for this workload is not straightforward. Solver performance may depend on many architectural properties, including single-thread performance, core count, cache capacity, memory bandwidth, memory latency, NUMA behavior, vector capabilities, and communication overhead between cores. At the same time, emerging computing platforms and specialized architectures may offer new opportunities for accelerating irregular optimization workloads.

In this research project, you will investigate how different hardware architectures affect the performance of large-scale MIQP-based scheduling and partitioning problems. The project will begin with a systematic benchmarking study across available computing platforms. Based on the observed bottlenecks, you will then develop and evaluate strategies that exploit the strengths of each architecture more effectively.

Possible research directions include:

• benchmarking CPUs with different core, cache, memory, and NUMA characteristics,
• analyzing solver behavior at the root relaxation and throughout the branch-and-bound tree,
• identifying which solver phases are limited by computation, memory access, synchronization, or search efficiency,
• evaluating many-core CPUs and heterogeneous computing platforms,
• investigating emerging architectures designed for irregular, graph-oriented, or combinatorial workloads,
• optimizing thread placement, memory allocation, solver parameters, and parallel search strategies,
• designing workload-aware strategies for selecting hardware and solver configurations,
• and exploring hybrid approaches in which selected solver components are offloaded to accelerators.

The project should go beyond reporting total runtime. Detailed profiling should be used to understand how hardware characteristics influence node processing speed, relaxation solving, cut generation, heuristic execution, memory consumption, synchronization overhead, and the evolution of primal and dual bounds.

A central goal is to determine whether different stages of the optimization process benefit from different hardware characteristics. This may enable adaptive strategies that select solver configurations dynamically, distribute work across heterogeneous resources, or assign specific subproblems to the architecture best suited to them.

Voraussetzungen

Robust and Explainable Cas13d Guide RNA Design

RNA-targeting CRISPR systems such as Cas13d have emerged as powerful tools for programmable transcriptome engineering. While STOA frameworks improve practical guide RNA design using sequence-only deep learning models and interpretable interfaces, important challenges remain unresolved. Current systems primarily optimize predicted efficacy, while real-world applications require balancing multiple objectives including specificity, robustness across transcripts, structural accessibility, and uncertainty estimation.

This project aims to develop a next-generation design automation framework that performs multi-objective and uncertainty-aware guide RNA optimization for Cas13d systems. The student will investigate how deep learning architectures can jointly model guide efficacy, off-target risk, transcript accessibility, and confidence estimation using only computationally obtainable information.

The project may include:

• designing improved hybrid architectures (Transformer/CNN/attention-based models),
• integrating RNA secondary structure predictions or accessibility priors,
• developing uncertainty-aware ranking methods,
• implementing multi-objective scoring and candidate ranking,
• creating explainability methods for sequence-level interpretation,
• evaluating generalization across transcripts or datasets,
• and optionally extending the interactive natural-language explanation interface.

The final outcome should be a deployable prototype that produces ranked and interpretable guide RNA candidates from raw transcript sequences while improving robustness and transparency in practical CRISPR RNA-targeting workflows.

Possible Research Questions

• Can uncertainty estimation improve trustworthiness in guide RNA ranking?
• How can off-target risk and efficacy be jointly optimized?
• Which sequence motifs or contextual interactions most strongly determine Cas13d activity?
• Can RNA structure-aware representations improve prediction using only computational inputs?
• How transferable are learned guide design principles across datasets or organisms?

Voraussetzungen

The intersection of artificial intelligence and hardware/system design is rapidly evolving. Many traditional problems in areas such as chip design, optimization, and system architecture are being revisited with modern machine learning techniques—yet there is still vast untapped potential for new ideas.

This open topic is aimed at students who want to go beyond predefined projects and instead explore their own research direction. We are particularly interested in novel and creative approaches, including (but not limited to):

• Applying machine learning to classical hardware or EDA problems
• Reinforcement learning or optimization for system design and scheduling
• AI-driven design space exploration or co-design approaches
• Using modern paradigms such as foundation models or autonomous research/optimization agents
• Completely new ideas that challenge existing workflows or assumptions

The goal is to identify promising research directions and develop them into meaningful projects, with the potential to grow into a thesis or even a research publication.

You will work closely with supervision to refine your idea, scope the problem, and develop a concrete research plan—but the starting point should come from you.

Voraussetzungen

Modern chip design involves increasingly complex optimization problems, in which millions of interdependent design decisions must be made under strict physical and performance constraints. One central problem in this area is macro placement: arranging large components, such as SRAM blocks and intellectual property modules, on a chip while jointly optimizing routing congestion, timing, power delivery, wirelength, and area utilization.

Macro placement is inherently challenging. It combines a highly discrete and constrained search space with multiple competing objectives and strong global dependencies between placement decisions. Classical placement methods have been refined over decades and remain highly effective, but recent advances in machine learning and generative modeling offer promising opportunities to complement or improve existing approaches.

In this research internship, you will develop and evaluate novel methods for macro placement and related combinatorial optimization problems. The goal is to investigate algorithms that can scale to large, highly constrained systems while producing high-quality solutions within realistic runtime limits.

Possible research directions include:

• reinforcement learning and graph neural network approaches,
• generative methods such as diffusion models for producing or refining placements,
• hybrid methods combining machine learning with classical heuristics or mathematical optimization,
• learned search, ranking, or proposal mechanisms,
• scalable approximation and local-search techniques,
• and improvements to established placement algorithms using modern machine-learning and optimization tooling.

A particular emphasis may be placed on exploring how generative models can learn distributions over high-quality placements, incorporate physical and design-rule constraints, and guide downstream search or refinement procedures. Rather than replacing established optimization methods entirely, such models may serve as initialization mechanisms, proposal generators, surrogate models, or components within hybrid optimization pipelines.

The developed approaches will be evaluated on representative macro-placement benchmarks using relevant physical-design metrics, including wirelength, congestion, timing-related proxies, constraint satisfaction, solution quality, scalability, and runtime.

Voraussetzungen

Recent advances in AI/ML models (e.g., large language models) demand unprecedented compute and memory resources, making efficient system design a central challenge. New approaches, such as energy-aware co-optimization of hardware architectures and workload execution, enable significant improvements in energy-delay efficiency and scalability .

This thesis builds on such optimization-driven frameworks and opens up a range of possible research directions. Rather than prescribing a fixed path, the goal is to let you explore and define your own contribution within this space, depending on your interests.

Possible directions include (but are not limited to):

• Optimization & Algorithms
  • Improve scalability and efficiency of optimization solvers (e.g., MIQP-based approaches)
  • Develop approximation, heuristic, or hybrid optimization techniques
  • Explore alternative formulations for large-scale design space exploration
• AI for Systems / Learning-Based Methods
  • Investigate reinforcement learning or learning-based approaches for scheduling, mapping, or architecture design
  • Compare learned vs. analytical optimization strategies
• Scalable Systems & Workloads
  • Extend analyses to extremely large workloads (e.g., LLM-scale systems)
  • Study trade-offs between performance, energy, and hardware constraints
• Hardware & Architecture Exploration
  • Analyze emerging architectures such as multi-chiplet systems
  • Explore memory hierarchies, interconnects, and power management strategies
• Tooling & Visualization
  • Develop intuitive interfaces or visual analytics tools for design space exploration
  • Make complex optimization results interpretable and interactive

The work can be adapted toward a more theoretical, systems-oriented, or practical/software-driven thesis. We aim to produce publishable research results, making this an excellent opportunity for students interested in academia or advanced R&D.

Voraussetzungen

Phase 1  — Complete a Compilation Pipeline

We provide a working compiler pipeline based on TVM. The first phase focuses on completing the remaining Python integration work needed to connect the different components into a fully end-to-end framework.

You will:

• Connect existing tools through Python
• Automate the end-to-end compilation workflow
• Test and debug the integrated pipeline
• Become familiar with compiler components and ML compilation workflows through hands-on development

Phase 2  — MLIR Toolchain for AMD Ryzen AI

After completing the integration, you will move toward extending an MLIR-based compilation toolchain targeting AMD Ryzen AI devices.

You will have the opportunity to:

• Learn and work with MLIR and LLVM
• Explore MLIR-based compilation and lowering pipelines
• Investigate code generation for AMD Ryzen AI
• Evaluate and optimize the generated code

This phase provides an opportunity to gain hands-on experience with modern compiler infrastructure and hardware-aware code generation.

Voraussetzungen

We are developing an open-source simulation framework for wavelength-routed Optical Networks-on-Chip (WRONoCs). The framework enables fast and accurate evaluation of optical communication quality by combining technology-calibrated photonic device models with circuit-level communication analysis. Our goal is to provide researchers with an accessible alternative to commercial photonic simulators for early-stage design exploration and communication quality assessment.

Project Timeline & Logistics

• The project is expected to be completed within approximately two - three months.
• I am looking for a student who can dedicate sufficient time to the project during this period.
• A complete software simulator and development framework will be provided at the beginning of the project.
• Since the current development environment is based on Windows, applicants are strongly preferred to have access to a Windows laptop or desktop.

Voraussetzungen

Project Overview

Digital Microfluidics (DMF) is a cutting-edge technology that enables the precise manipulation of minute fluid volumes (droplets) via electrical actuation. We currently have a functional web-based design tool that allows researchers to create custom PCB-based and glass-based DMF chips. This platform streamlines the transition from concept to manufacturable hardware by providing features like custom electrode placement, automated routing, and experiment definition.

We are looking for motivated students to join our follow-up project. The goal is to extend the platform's functional modules and refine the core routing algorithms to handle increasingly complex chip architectures.

Tasks

As a student on this project, you will focus on two primary areas:

1. Platform Extension & Feature Enhancement

• Integrated Path Planning: Develop an automated droplet path planning feature where users can select start and end points, and the system generates the optimal movement sequence.
• Functional Module Libraries: Create templates and interfaces for specialized biological and chemical detection modules to improve design efficiency for specific experimental scenarios.
• Advanced UI/UX: Enhance the interactive editor, building upon existing features like "undo/redo," "copy/paste," and the "parallel electrode" batch processing system.

2. Routing Algorithm Refinement

• Algorithm Optimization: Work with our existing WebAssembly (WASM) and Web Worker-based routing engine to improve performance and success rates for high-density designs.
• Geometric Refinement: Modify the grid-based routing and collision detection logic to support finer electrode spacings and complex trace widths.
• Via Management: Refine the dynamic via cost mechanisms to optimize vertical interconnections between PCB layers.

Technical Environment

You will work with a modern, high-performance tech stack:

• Frontend: Vue 3, Element Plus, and SVG for vector graphics rendering.
• Core Logic: C++ (compiled to WebAssembly) for heavy computational tasks.
• Communication: Web Serial API for real-time hardware interfacing.
• Hardware Integration: Exporting KiCad-compatible files for physical PCB manufacturing.

Requirements

• Strong interest in Electronic Design Automation (EDA) or Microfluidics.
• Proficiency in JavaScript/TypeScript (preferably Vue 3) or C++.
• Basic understanding of geometric algorithms or PCB design is a plus.

Robust and Explainable Cas13d Guide RNA Design

RNA-targeting CRISPR systems such as Cas13d have emerged as powerful tools for programmable transcriptome engineering. While STOA frameworks improve practical guide RNA design using sequence-only deep learning models and interpretable interfaces, important challenges remain unresolved. Current systems primarily optimize predicted efficacy, while real-world applications require balancing multiple objectives including specificity, robustness across transcripts, structural accessibility, and uncertainty estimation.

This project aims to develop a next-generation design automation framework that performs multi-objective and uncertainty-aware guide RNA optimization for Cas13d systems. The student will investigate how deep learning architectures can jointly model guide efficacy, off-target risk, transcript accessibility, and confidence estimation using only computationally obtainable information.

The project may include:

• designing improved hybrid architectures (Transformer/CNN/attention-based models),
• integrating RNA secondary structure predictions or accessibility priors,
• developing uncertainty-aware ranking methods,
• implementing multi-objective scoring and candidate ranking,
• creating explainability methods for sequence-level interpretation,
• evaluating generalization across transcripts or datasets,
• and optionally extending the interactive natural-language explanation interface.

The final outcome should be a deployable prototype that produces ranked and interpretable guide RNA candidates from raw transcript sequences while improving robustness and transparency in practical CRISPR RNA-targeting workflows.

Possible Research Questions

• Can uncertainty estimation improve trustworthiness in guide RNA ranking?
• How can off-target risk and efficacy be jointly optimized?
• Which sequence motifs or contextual interactions most strongly determine Cas13d activity?
• Can RNA structure-aware representations improve prediction using only computational inputs?
• How transferable are learned guide design principles across datasets or organisms?

Voraussetzungen

The intersection of artificial intelligence and hardware/system design is rapidly evolving. Many traditional problems in areas such as chip design, optimization, and system architecture are being revisited with modern machine learning techniques—yet there is still vast untapped potential for new ideas.

This open topic is aimed at students who want to go beyond predefined projects and instead explore their own research direction. We are particularly interested in novel and creative approaches, including (but not limited to):

• Applying machine learning to classical hardware or EDA problems
• Reinforcement learning or optimization for system design and scheduling
• AI-driven design space exploration or co-design approaches
• Using modern paradigms such as foundation models or autonomous research/optimization agents
• Completely new ideas that challenge existing workflows or assumptions

The goal is to identify promising research directions and develop them into meaningful projects, with the potential to grow into a thesis or even a research publication.

You will work closely with supervision to refine your idea, scope the problem, and develop a concrete research plan—but the starting point should come from you.

Voraussetzungen

Recent advances in AI/ML models (e.g., large language models) demand unprecedented compute and memory resources, making efficient system design a central challenge. New approaches, such as energy-aware co-optimization of hardware architectures and workload execution, enable significant improvements in energy-delay efficiency and scalability .

This thesis builds on such optimization-driven frameworks and opens up a range of possible research directions. Rather than prescribing a fixed path, the goal is to let you explore and define your own contribution within this space, depending on your interests.

Possible directions include (but are not limited to):

• Optimization & Algorithms
  • Improve scalability and efficiency of optimization solvers (e.g., MIQP-based approaches)
  • Develop approximation, heuristic, or hybrid optimization techniques
  • Explore alternative formulations for large-scale design space exploration
• AI for Systems / Learning-Based Methods
  • Investigate reinforcement learning or learning-based approaches for scheduling, mapping, or architecture design
  • Compare learned vs. analytical optimization strategies
• Scalable Systems & Workloads
  • Extend analyses to extremely large workloads (e.g., LLM-scale systems)
  • Study trade-offs between performance, energy, and hardware constraints
• Hardware & Architecture Exploration
  • Analyze emerging architectures such as multi-chiplet systems
  • Explore memory hierarchies, interconnects, and power management strategies
• Tooling & Visualization
  • Develop intuitive interfaces or visual analytics tools for design space exploration
  • Make complex optimization results interpretable and interactive

The work can be adapted toward a more theoretical, systems-oriented, or practical/software-driven thesis. We aim to produce publishable research results, making this an excellent opportunity for students interested in academia or advanced R&D.

Voraussetzungen