Although digital circuits usually comprise the largest part in integrated circuits, analog components require a much larger part of the design effort. To that end, analog design tools are vital for the industry. Industry norm are simulation tools and optimization tools.  In recent years, further steps in the implementation process, such as circuit synthesis and direct performance estimation via machine learning techniques, have been focused on in research.  In this work, a testbench for circuits resulting from such novel approaches  will be implemented. It will comprise an interface to classical simulation tools, as well as complete automation of the testing process.

Although digital circuits usually comprise the largest part in integrated circuits, analog components require a much larger part of the design effort. To that end, analog design tools are vital for the industry. Industry norm are simulation tools and optimization tools.  In recent years, solutions for traditionally hard to solve problems, such as circuit synthesis, have been successfully demonstrated in research. One of those solutions [1], developed at the EDA chair, uses the implicit hierarchy within analog circuits to split the problem into several smaller problems, which can be handled efficiently to produce performance equations and synthesize analog circuits.  In this work, an interface to the tool should be programmed, to expose its performance computation capabilities to the outside of the framework.

References:

• Basic knowledge of circuit design
• Experience with C++ or Python highly recommended

Machine Learning on the edge is becoming more and more popular nowadays. Especially for safety critical applications it is not acceptable to have any deviation of model outputs caused by the deployment method while other application might accept differences to the golden reference outputs to some degree.

Our TVM deployment flow is mainly based on the MLonMCU (https://github.com/tum-ei-eda/mlonmcu) tool. While it already supports validating model outputs, this functionality is rather limited.

Task Description:

• Goal: Reimplement the validation feature in MLonMCU to be more flexible and accurate
• Configuration: In additionon to bit-excact equivalences, the user may also allow deviations in some degree (absolute/relative delta)
• Flexibility: Provide an generic interface supporting several target-specific implementations (Offline: data compiled in ROM, Online: data sent via Semihosting, UART,...)
• Accuracy: Allow comparing intermediate values (between layers) in addition to just model outputs.

• Basic Knownledge of Machine Learning
• Experience with Embedded C programming
• Good Python Coding skills
• Ideally experience using TVM Machinne Learning Framework

DXF is short for Drawing Exchange Format or Drawing Interchange Format and is a vector file type. Engineers, designers, and architects often use the DXF format for drawings during product design. DXF is widely used in industrial production. Many devices such as printers, laser cutters, CNC machining, etc. accept DXF format as input. In this project, we would like you to implement a generic DXF library that can be used by different software to produce designs in DXF format. 

• Knowledge and experience in web design and web development or desktop application development
• Good understanding of JavaScript and PHP or Java Spring Boot or the wiliness to learn them
• Basic knowledge of Vue.js (or other frontend frameworks) or object-oriented programming or the cunning to know them
• Solution-oriented thinking

Semantic image synthesis based only on adversarial supervision has recently made remarkable progress. Different to traditional GAN-based approaches, "OASIS" has redesigned the purpose of the discriminator as a N+1 semantic segmentation network, directly using the given semantic label maps as the ground truth for training. By providing stronger supervision to the discriminator as well as to the generator through spatially- and semantically-aware discriminator feedback, OASIS has achieved SOA performance and remains a strong baseline even for powerful diffusion-based models, such as https://arxiv.org/pdf/2207.00050.pdf. 

Despite its great success, it is well known that semantic image synthesis based only on semantic maps often fails in complex environments where multiple instances occlude each other.

The goal of this work is to investigate whether OASIS can be extended to the panoptic case, both from the perspective of the learning objective and the network architecture.

Your work:

• Literature review of state-of-the-art semantic/ panoptic-aware image synthesis methods, e.g., https://arxiv.org/abs/2012.04781, https://arxiv.org/pdf/2004.10289.pdf.
• Analysis and identification of suitable panoptic segmentation backbones/ learning objectives. Possible starting point: https://arxiv.org/pdf/2207.04044.pdf.
• Development of a prototype based on https://github.com/boschresearch/OASIS + evaluation thereof and comparison to the current state-of-the-art.
• Optional: opportunity to contribute to publications.

Requirements:

• Solid background in machine learning, as well as Python and common deep learning libraries such as TensorFlow or PyTorch.
• Self-motivation.

Transformer-based transform coding has shown to attain a better rate-distortion-computation trade-off compared to existing solutions. Unlike CNNs, the self-attention mechanism within transformer blocks provides a more general compute paradigm that greatly helps to capture long-range dependencies. However, its great potential is accompanied by a quadratic complexity, which is why a variety of efficient alternatives have been proposed, all with their respective advantages and disadvantages.

Recent work has primarily focused on windowed attention, e.g., “Swin Transformer”, thanks to its hierarchical design and excellent scaling properties. It remains however unclear how much the attention window pattern affects the overall compression performance.

The goal of this work is to analyze and compare current transformer-based solutions specifically suited for dense prediction tasks/ image/ video compression.

Your work:

• Literature review of state-of-the-art transformer-based coding methods, e.g., https://openreview.net/pdf?id=IDwN6xjHnK8.
• Analysis and identification of efficient attention mechanisms suitable for dense prediction tasks/ image/video compression. Possible starting point: https://github.com/tensorflow/compression/discussions/151
• Development of several prototypes based on https://github.com/Nikolai10/SwinT-ChARM + evaluation thereof and comparison to the current state-of-the-art.
• Optional: opportunity to contribute to publications.

Requirements:

• Solid background in machine learning, as well as Python and common deep learning libraries such as TensorFlow or PyTorch.
• Self-motivation.

Siehe beigefügtes pdf

Although digital circuits usually comprise the largest part in integrated circuits, analog components require a much larger part of the design effort. To that end, analog design tools are vital for the industry. Industry norm are simulation tools and optimization tools.  In recent years, solutions for traditionally hard to solve problems, such as circuit synthesis, have been successfully demonstrated in research. One of those solutions [1], developed at the EDA chair, uses the implicit hierarchy within analog circuits to split the problem into several smaller problems, which can be handled efficiently to produce performance equations and synthesize analog circuits.  In this work, an interface to the tool should be programmed, to expose its performance computation capabilities to the outside of the framework. Additionally, another simulation interface to industry design tools Virtuoso and WiCkeD will be implemented, to corroborate the results and enable further analysis.

References:
[1] Inga Abel and Helmut Graeb. 2022. FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition. ACM Trans. Des. Autom. Electron. Syst. 27, 6, Article 63 (November 2022), 27 pages. https://arxiv.org/abs/2101.07517

• Basic knowledge of circuit theory
• Experience with C++ or Python highly recommended
• First contact with Cadence Virtuoso beneficial

Machine learning is getting strong attention in circuit design and electronic design automation. One use case for it would be the generation of accurate power models for intellectual property (IP) blocks [1]. The providers of these blocks are interested in keeping their knowledge about optimized designs secret(black-box IP blocks). This limits the possibility for power modeling, as classical methods would require and reveal information about the structure of the implementation. Here, machine learning can support in generating opaque power models. Models using graph attention networks [2], feed-forward neural networks, reservoir computing or deep spline networks [3] could be used.

But, it is questionable, how opaque are the resulting models? If one would consider single modifications on a circuit netlist (e.g. optimizing only a single connection). Would this change also be observable in the differences between the resulting power models (e.g. as only very small regions of the model would change)? If this is the case, one could maybe infer from a set of simple modifications a significant amount of information about the original circuit design.

The goal of this project would be to investigate these questions. Therefore, in an existing framework for power model generation, different ML method need to be implemented. Then, for suitable benchmark designs, such single optimizations steps should be generated and the resulting power models investigated.

[1] ZHANG, Yanqing; REN, Haoxing; KHAILANY, Brucek. GRANNITE: Graph neural network inference for transferable power estimation. In: 2020 57th ACM/IEEE Design Automation Conference (DAC). IEEE, 2020. S. 1-6.

[2] XIE, Zhiyao, et al. Pre-Placement Net Length and Timing Estimation by Customized Graph Neural Network. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022.

[3] BOHRA, Pakshal, et al. Learning activation functions in deep (spline) neural networks. IEEE Open Journal of Signal Processing, 2020, 1. Jg., S. 295-309.

• Profound knowledge in machine learning (preferably in reservoir computing and deep neural networks)
• Knowledge of digital circuit design (preferably also in the ASIC design flow)
• Good knowledge in python
• Ability to work independently

DXF is short for Drawing Exchange Format or Drawing Interchange Format and is a vector file type. Engineers, designers, and architects often use the DXF format for drawings during product design. DXF is widely used in industrial production. Many devices such as printers, laser cutters, CNC machining, etc. accept DXF format as input. In this project, we would like you to implement a generic DXF library that can be used by different software to produce designs in DXF format. 

• Knowledge and experience in web design and web development or desktop application development
• Good understanding of JavaScript and PHP or Java Spring Boot or the wiliness to learn them
• Basic knowledge of Vue.js (or other frontend frameworks) or object-oriented programming or the cunning to know them
• Solution-oriented thinking

Semantic image synthesis based only on adversarial supervision has recently made remarkable progress. Different to traditional GAN-based approaches, "OASIS" has redesigned the purpose of the discriminator as a N+1 semantic segmentation network, directly using the given semantic label maps as the ground truth for training. By providing stronger supervision to the discriminator as well as to the generator through spatially- and semantically-aware discriminator feedback, OASIS has achieved SOA performance and remains a strong baseline even for powerful diffusion-based models, such as https://arxiv.org/pdf/2207.00050.pdf. 

Despite its great success, it is well known that semantic image synthesis based only on semantic maps often fails in complex environments where multiple instances occlude each other.

The goal of this work is to investigate whether OASIS can be extended to the panoptic case, both from the perspective of the learning objective and the network architecture.

Your work:

• Literature review of state-of-the-art semantic/ panoptic-aware image synthesis methods, e.g., https://arxiv.org/abs/2012.04781, https://arxiv.org/pdf/2004.10289.pdf.
• Analysis and identification of suitable panoptic segmentation backbones/ learning objectives. Possible starting point: https://arxiv.org/pdf/2207.04044.pdf.
• Development of a prototype based on https://github.com/boschresearch/OASIS + evaluation thereof and comparison to the current state-of-the-art.
• Optional: opportunity to contribute to publications.

Requirements:

• Solid background in machine learning, as well as Python and common deep learning libraries such as TensorFlow or PyTorch.
• Self-motivation.

Transformer-based transform coding has shown to attain a better rate-distortion-computation trade-off compared to existing solutions. Unlike CNNs, the self-attention mechanism within transformer blocks provides a more general compute paradigm that greatly helps to capture long-range dependencies. However, its great potential is accompanied by a quadratic complexity, which is why a variety of efficient alternatives have been proposed, all with their respective advantages and disadvantages.

Recent work has primarily focused on windowed attention, e.g., “Swin Transformer”, thanks to its hierarchical design and excellent scaling properties. It remains however unclear how much the attention window pattern affects the overall compression performance.

The goal of this work is to analyze and compare current transformer-based solutions specifically suited for dense prediction tasks/ image/ video compression.

Your work:

• Literature review of state-of-the-art transformer-based coding methods, e.g., https://openreview.net/pdf?id=IDwN6xjHnK8.
• Analysis and identification of efficient attention mechanisms suitable for dense prediction tasks/ image/video compression. Possible starting point: https://github.com/tensorflow/compression/discussions/151
• Development of several prototypes based on https://github.com/Nikolai10/SwinT-ChARM + evaluation thereof and comparison to the current state-of-the-art.
• Optional: opportunity to contribute to publications.

Requirements:

• Solid background in machine learning, as well as Python and common deep learning libraries such as TensorFlow or PyTorch.
• Self-motivation.

In this work the design and integration of hardware loop acceleration should be studied in the context of Embedded Machine Learning. The steps of this thesis can be summarized as follows:

• Survey the current state-of-the art of zero-overhead loops in research (and industry)
• Introduce the basic knowledge/theory required to understand the concept of hardware loop acceleration
• Propose and implement an hardware architecture for a simple hardware loop accelerator
• Integrate your hardware loop acceleration into a RISC-V VP run in the ETISS simulator
• Produce preliminary benchmarks to compare implementations with and without hardware loop support.
• Optional: Integrate the hardware loop intrinsics in the TVM ML compiler flow to automatically generate accelerated programs.
• Optional: Benchmark your zero-overhead loop implementation on various real-world ML models.

• Good knownledge on processor architectures (ideally RISC-V)
• Experience with Embedded Machine Learning e.g. Training (Keras/TensorFlow), Embedded Software Development (C, Assembly) and Hardware Accelerator Design (VHDL/Verilog)
• Experience with C/C++
• Optional: Experience with CoreDSL2
• Optional: Experience with the TVM ML Compiler flow
• Optional: Experience with the ETISS simulator

RISC-V is a new, open instruction set architecture (ISA) that, as a core feature, can be extended with special instructions to customize embedded processors to special applications such as frm the control and machine learning domain.

We already developed a customizable simulator named ETISS, that can quickly evaluate the benefit of special instructions for a given application. Next to the core, also the compiler and assembler support for creating a binary from embedded C code is required by designers to exploit performance benefits of special instructions.

In this thesis, a method and implementation should be developed in order to automatically generate patches for the LLVM and GCC toochain from a formal definition of a special instruction. There are various levels of special instruction support possible in the toolchain, that should be explored within this thesis.

DXF is short for Drawing Exchange Format or Drawing Interchange Format and is a vector file type. Engineers, designers, and architects often use the DXF format for drawings during product design. DXF is widely used in industrial production. Many devices such as printers, laser cutters, CNC machining, etc. accept DXF format as input. In this project, we would like you to implement a generic DXF library that can be used by different software to produce designs in DXF format. 

• Knowledge and experience in web design and web development or desktop application development
• Good understanding of JavaScript and PHP or Java Spring Boot or the wiliness to learn them
• Basic knowledge of Vue.js (or other frontend frameworks) or object-oriented programming or the cunning to know them
• Solution-oriented thinking

The required steps can be described as follows:

• Get used to the MLonMCU Benchmarking flow
• Propose a concept for a remote execution of benchmarks
• Implement remote execution protocol
• Add more features to improve benchmarking throughput
• Add detailed documentation

• Experience with networking protocols
• Good Python programming
• Ideally experience working with UNIX-like operating systems

The ETISS Simulator can be used for simulating programs compiled for a variety of targets on a instruction level. The goal of the work is to make performance analysis (profiling) possible with ETISS on several abstraction levels.

Task Description:

• Survey state-of-the art profiling methods for embedded SW
• Get used to existing set of tools (ETISS, Tracer, RISC-V SW Compiler)
• Generate Instruction Traces of Program Execution with ETISS (already implemented)
• Analyse Trace to count how often specific parts of code are executed on several levels: Instruction, "Basic Block", (For ML workloads: per Layer)
• Visualize Profiling Results
• Convert trace or profiling result to be compatible with existing (GUI-based) profiling tools

• Knownledge of C++ programming language
• Preferably experience with Python Scripting
• Experience with Embedded SW Development (e.g. ARM/RISC-V)

Although digital circuits usually comprise the largest part in integrated circuits, analog components require a much larger part of the design effort. To that end, analog design tools are vital for the industry. Industry norm are simulation tools and optimization tools.  In recent years, solutions for traditionally hard to solve problems, such as circuit synthesis, have been successfully demonstrated in research. One of those solutions [1], developed at the EDA chair, uses the implicit hierarchy within analog circuits to split the problem into several smaller problems, which can be handled efficiently to produce performance equations and synthesize analog circuits.  In this work, an interface to the tool should be programmed, to expose its performance computation capabilities to the outside of the framework. Additionally, another simulation interface to industry design tools Virtuoso and WiCkeD will be implemented, to corroborate the results and enable further analysis.

References:
[1] Inga Abel and Helmut Graeb. 2022. FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition. ACM Trans. Des. Autom. Electron. Syst. 27, 6, Article 63 (November 2022), 27 pages. https://arxiv.org/abs/2101.07517

• Basic knowledge of circuit theory
• Experience with C++ or Python highly recommended
• First contact with Cadence Virtuoso beneficial

Machine Learning on the edge is becoming more and more popular nowadays. Especially for safety critical applications it is not acceptable to have any deviation of model outputs caused by the deployment method while other application might accept differences to the golden reference outputs to some degree.

Our TVM deployment flow is mainly based on the MLonMCU (https://github.com/tum-ei-eda/mlonmcu) tool. While it already supports validating model outputs, this functionality is rather limited.

Task Description:

• Goal: Reimplement the validation feature in MLonMCU to be more flexible and accurate
• Configuration: In additionon to bit-excact equivalences, the user may also allow deviations in some degree (absolute/relative delta)
• Flexibility: Provide an generic interface supporting several target-specific implementations (Offline: data compiled in ROM, Online: data sent via Semihosting, UART,...)
• Accuracy: Allow comparing intermediate values (between layers) in addition to just model outputs.

• Basic Knownledge of Machine Learning
• Experience with Embedded C programming
• Good Python Coding skills
• Ideally experience using TVM Machinne Learning Framework

Based on existing implementation of Network Architecture Search Framework.

Task Description

• Improve existing muNAS implementation
• Extend muNAS by adding deployment related metrics and constraints

The required steps can be described as follows:

• Get used to the MLonMCU Benchmarking flow
• Propose a concept for a remote execution of benchmarks
• Implement remote execution protocol
• Add more features to improve benchmarking throughput
• Add detailed documentation

• Experience with networking protocols
• Good Python programming
• Ideally experience working with UNIX-like operating systems

RISC-V is a new, open instruction set architecture (ISA) that, as a core feature, can be extended with special instructions to customize embedded processors to special applications such as frm the control and machine learning domain.

We already developed a customizable simulator named ETISS, that can quickly evaluate the benefit of special instructions for a given application. Next to the core, also the compiler and assembler support for creating a binary from embedded C code is required by designers to exploit performance benefits of special instructions.

In this thesis, a method and implementation should be developed in order to automatically generate patches for the LLVM and GCC toochain from a formal definition of a special instruction. There are various levels of special instruction support possible in the toolchain, that should be explored within this thesis.

Although digital circuits usually comprise the largest part in integrated circuits, analog components require a much larger part of the design effort. To that end, analog design tools are vital for the industry. Industry norm are simulation tools and optimization tools.  In recent years, further steps in the implementation process, such as circuit synthesis and direct performance estimation via machine learning techniques, have been focused on in research.  In this work, a testbench for circuits resulting from such novel approaches  will be implemented. It will comprise an interface to classical simulation tools, as well as complete automation of the testing process.

Although digital circuits usually comprise the largest part in integrated circuits, analog components require a much larger part of the design effort. To that end, analog design tools are vital for the industry. Industry norm are simulation tools and optimization tools.  In recent years, solutions for traditionally hard to solve problems, such as circuit synthesis, have been successfully demonstrated in research. One of those solutions [1], developed at the EDA chair, uses the implicit hierarchy within analog circuits to split the problem into several smaller problems, which can be handled efficiently to produce performance equations and synthesize analog circuits.  In this work, an interface to the tool should be programmed, to expose its performance computation capabilities to the outside of the framework.

References:

• Basic knowledge of circuit design
• Experience with C++ or Python highly recommended

DXF is short for Drawing Exchange Format or Drawing Interchange Format and is a vector file type. Engineers, designers, and architects often use the DXF format for drawings during product design. DXF is widely used in industrial production. Many devices such as printers, laser cutters, CNC machining, etc. accept DXF format as input. In this project, we would like you to implement a generic DXF library that can be used by different software to produce designs in DXF format. 

• Knowledge and experience in web design and web development or desktop application development
• Good understanding of JavaScript and PHP or Java Spring Boot or the wiliness to learn them
• Basic knowledge of Vue.js (or other frontend frameworks) or object-oriented programming or the cunning to know them
• Solution-oriented thinking

Based on existing implementation of Network Architecture Search Framework.

Task Description

• Improve existing muNAS implementation
• Extend muNAS by adding deployment related metrics and constraints