Physical Design for Microfluidic Large-Scale Integration with Partitioning and Floorplanning

DFG Research Grant (since 2023)

• Exploration of mLSI design partitioning and floorplanning to solve the physical design problem in a hierarchical manner.

Bandwidth Maximization and Allocation for Wavelength-Routed Optical Networks-on-Chip (WRONoC)

DFG Research Grant (since 2023)

• WRONoC topology synthesis considering bandwidth maximization and allocation.

Design and Integration of Test Module for Microfluidic Large-Scale Integration (mLSI)

DFG Research Grant (since 2021)

• Design and integration of microfluidic test modules, as well as the synthesis of testable designs.

Combining Topology Synthesis and Physical Design for Wavelength-Routed Optical Networks-on-Chip (WRONoC) — Design Automation Using Physical Layout Templates

DFG Research Grant (since 2020)

• Development of comprehensive template-based design automation methods for wavelength-routed optical network-on-chip

Sicherer Automatischer Software-Entwurf für Industrieanlagen (SAFE4I)

BMBF project: 1.10.2017-30.9.2021

In this project we work on the automatic generation of software safety mechanisms

Kosten-Effiziente Smart-System Software-Synthese (COMPACT)

ITEA 3 project: 1.9.2017-31.8.2020

Here we work on methods to onchip de-compress software and data for small IoT nodes.

Automatic firmware design for application-specific electronic systems (ConFIRM)

BMBF Cluster-Project (01.01.2017-31.12.2019)

• Optimization of the HW/SW Interface
• Automatic generation of low memory footprint firmware for resource-constraint systems

Invasive Computing (InvasIC)

DFG Transregional Collaborative Research Centre 89 (01.07.2010-30.06.2022)

• Hardware Monitoring System and Design Optimisation for Invasive Architectures
• Runtime Verification and Monitoring

Automatic Analysis of PCB Schematic Designs

Collaborative project with Huawei (16.11.2021-15.05.2022)

RoMulus: Robuste Multisensorik zur Zustandsüberwachung in Industrie-4.0-Anwendungen

EffektiV: Efficient Fault Simulation using virtual Prototypes for Qualification of Intelligent Motion-Control-Systems in Industrial Automation

BMBF Project Subcontractor from Infineon Technologies AG (1.10.2013-30.9.2016)

• Unit Test Framework with Fault Injection to test robustness of Automotive Firmware
• Fault Injection Framework to Test Impact of soft Errors in Processor Pipelines on Embedded Software  Execution

Resilient Integrated Systems Work Areas (RESIST)

BMBF Collaborative Project (1.1.2014-31.12.2016)

•  Monitors for analog-/Mixed Signal Components

Application of a Generative Grammar for the Automated Architectural Exploration of Digital System-on-Chip (SoC) Platforms

DFG Research Grant (1.1.2014 - 31.12.2016)

• Application and Theory of Graph Grammars and Graph Re-Writing
• Integration of IP blocks in SoCs using IP-Xact Metamodels
• Design Space Exploration of SoCs

Netlist-driven Design of MEMS for Applications in Optics and Robotics (MEMS2015)

BMBF Collaborative Project (1.7.2012-30.06.2015)

• Structural analysis and sizing of MEMS

Methods for automatic optimization of analogue integrated circuits with regard to ageing

DFG Research Grant (01.02.2012-31.01.2015)

Design and Architectures of Dependable Embedded Systems (SPP1500)

DFG Priority Programme 1500 (01.2011-12.2015)

• Lifting Device-Level Characteristics for Error Resilient System Level Design: A Crosslayer Approach

Design for RELIABILITY of SoCs for Applications like Transportation, Medical, and Industrial Automation (RELY)

BMBF/CATRENE Collaborative Project (01.05.2011-30.04.2014)

• Methods to consider aging in the mixed-signal design flow (with Infineon Technologies)
• Abstract reliability models for digital circuit design (with Infineon Technologies)

Secure Systems by Seamless Verification (SANITAS)

BMBF Collaborative Project (01.10.2009-30.09.2012)

• Optimized Modeling of non-functional properties for TLM/TLM+ models (with Infineon Technologies)

Design of Robust Nano-Electronic Systems (ROBUST)

BMBF Cluster Project (01.04.2009-31.03.2012)

• Analysis methods for digital modules (with Infineon Technologies)
• Robustness optimization on gate level (with Infineon Technologies)

Highly Optimized Design Methods for Yield and Reliability (HONEY)

BMBF Collaborative Project (01.12.2007-30.11.2010)

• Tolerance Pareto Optimization (with MunEDA)
• Reliability analysis on gate level (with Infineon Technologies)

Technology based Modeling and Analysis at the 65-nm Node Considering Statistical Spreads (SIGMA65)

BMBF Collaborative Project (01.10.2006-31.12.2009)

• Statistical Static Timing Analysis (with Infineon Technologies)

Analog/Mixed-Signal Design for Test

Infineon Technologies (01.11.2006-31.10.2009)

Verification of Analog Circuits (VERONA)

BMBF Collaborative Project (01.06.2006-31.05.2009)

• Pareto Optimization (with MunEDA)

Structural Analysis of Analog Circuits (SAMS)

BMBF Cluster Project (01.11.2003-31.10.2006)

• Fast Evaluation of Structural Variants

Design and Design Methodology of Embedded Systems (SPP1040)

DFG Priority Programme 1040 (1997-2004)

• Simulation-based test design for mixed-signal systems

Analogue enhancements for a system to silicon automated design (ANASTASIA+)

BMBF Cluster Project (01.12.2000-31.12.2002)

• Sizing of Analog Circuits (with Infineon Technologies)