- LightR: A Fault-Tolerant Wavelength-Routed Optical Networks-on-Chip Topology. MDPI Applied Sciences 13 (15), 2023, 8871 mehr…
- Accurate Infinite-order Crosstalk Calculation for Optical Networks-on-Chip. IEEE/OSA Journal of Lightwave Technology (JLT) 41 (1), 2023, 4 - 16 mehr…
- XRing: A Crosstalk-Aware Synthesis Method for Wavelength-Routed Optical Ring Routers. Design, Automation and Test in Europe (DATE), 2023 mehr…
- Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 41 (12), 2022, 5261 - 5274 mehr…
- Efficiency-Oriented Design Automation Methods for Wavelength-Routed Optical Network-on-Chip. In: Silicon Photonics for High-Performance Computing and Beyond. CRC Press, 2021, 177 -- 187 mehr…
- FAST: A Fast Automatic Sweeping Topology Customization Method for Application-Specific Wavelength-Routed Optical NoCs. Design, Automation and Test in Europe (DATE), 2021 mehr…
- ToPro: A Topology Projector and Waveguide Router for Wavelength-Routed Optical Networks-on-Chip. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2021 mehr…
- Light: A Scalable and Efficient Wavelength-Routed Optical Networks-On-Chip Topology. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), 2021 mehr…
- PSION+: Combining logical topology and physical layout optimization for Wavelength-Routed ONoCs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020 mehr…
- Maximizing the Communication Parallelism for Wavelength-Routed Optical Networks-on-Chips. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), 2020 mehr…
- PSION 2: Optimizing Physical Layout of Wavelength-Routed ONoCs for Laser Power Reduction. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2020 mehr…
- Wavelength-Routed Optical NoCs: Design and EDA — State of the Art and Future Directions. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2019 mehr…
- PSION: Combining logical topology and physical layout optimization for Wavelength-Routed ONoCs. ACM/SIGDA International Symposium on Physical Design (ISPD), 2019 mehr…
- CustomTopo: A Topology Generation Method for Application-Specific Wavelength-Routed Optical NoCs. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2018 mehr…
Optical Networks-on-Chip (ONoC)
CLASSICAL WRONoC SYNTHESIS: FROM TOPOLOGY GENERATION TO PHYSICAL DESIGN
Over the past decade, our researchers have developed a series of design automation tools for wavelength-routed optical networks-on-chip (WRONoCs): from topology generation to physical design. In our tools, we model the design automation problems as linear and quadratic optimization problems and apply corresponding optimization methods and algorithms.
Specifically, our topology generation tool CustomTopo synthesizes customized application-specific WRONoC topologies with a focus on minimizing network redundancy; and our physical design tools including PROTON, PROTON+, PLATON and PlanarONoC focus on insertion loss minimization by reducing waveguide crossings and waveguide lengths.
PSION: Combining logical topology and physical layout optimization of Wavelength-Routed Optical Networks-on-Chip
The design of WRONoCs is an optimization process that seeks to minimize electrical & optical power usage (among other metrics) while maximizing network performance (e.g. throughput of the optical channels). Traditionally, this process is done in two steps: first the logical topology of the network is created according to network requirements (eg. communication matrix), then the elements in the topology are placed & routed (P&R) according to the physical constraints of the integrated circuit. Unfortunately, this may lead to suboptimal designs because the dependency between logical topology and physical layout is inherently bi-directional, i.e. logical topology constraints dictate P&R results, but P&R constraints also influence the best logical topology.
The PSION family of tools seeks to perform optimization of both steps at once for the optimization functions relevant in WRONoC design, going from the underlying WRONoC design requirements directly to a finished WRONoC design.
Light: A Scalable and Efficient Wavelength-Routed Optical Networks-On-Chip Topology
WRONoCs are known for delivering collision- and arbitration-free on-chip communication in many-cores systems. While appealing for low latency and high predictability, WRONoCs are challenged by scalability concerns caused by high microring resonator (MRR) usage and the mismatch with realistic physical constraints.
To address these problems, we have proposed an N x (N - 1) WRONoC topology: Light with a 4 x 3 router Hash as the basic building block, and a simple but efficient approach to configure the resonant wavelength for each MRR. Compared with state-of-the-art topologies, Light reduces the MRR usage by more than a half and avoids additional waveguide crossings or detours during physical implementation. Experimental results show that Light outperforms state-of-the-art topologies in terms of enhancing signal-to-noise ratio (SNR) and reducing insertion loss, especially for large-scale networks. Furthermore, Light has great potential in application-specific WRONoCs. Thus, our further target is to adapt Light to support different kinds of applications with low insertion loss and high signal quality.